1*4882a593SmuzhiyunDevice tree bindings for Marvell PXA SSP ports 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun - compatible: Must be one of 6*4882a593Smuzhiyun mrvl,pxa25x-ssp 7*4882a593Smuzhiyun mvrl,pxa25x-nssp 8*4882a593Smuzhiyun mrvl,pxa27x-ssp 9*4882a593Smuzhiyun mrvl,pxa3xx-ssp 10*4882a593Smuzhiyun mvrl,pxa168-ssp 11*4882a593Smuzhiyun mrvl,pxa910-ssp 12*4882a593Smuzhiyun mrvl,ce4100-ssp 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun - reg: The memory base 15*4882a593Smuzhiyun - dmas: Two dma phandles, one for rx, one for tx 16*4882a593Smuzhiyun - dma-names: Must be "rx", "tx" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample for PXA3xx: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun ssp0: ssp@41000000 { 22*4882a593Smuzhiyun compatible = "mrvl,pxa3xx-ssp"; 23*4882a593Smuzhiyun reg = <0x41000000 0x40>; 24*4882a593Smuzhiyun ssp-id = <1>; 25*4882a593Smuzhiyun interrupts = <24>; 26*4882a593Smuzhiyun clock-names = "pxa27x-ssp.0"; 27*4882a593Smuzhiyun dmas = <&dma 13 28*4882a593Smuzhiyun &dma 14>; 29*4882a593Smuzhiyun dma-names = "rx", "tx"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun ssp1: ssp@41700000 { 33*4882a593Smuzhiyun compatible = "mrvl,pxa3xx-ssp"; 34*4882a593Smuzhiyun reg = <0x41700000 0x40>; 35*4882a593Smuzhiyun ssp-id = <2>; 36*4882a593Smuzhiyun interrupts = <16>; 37*4882a593Smuzhiyun clock-names = "pxa27x-ssp.1"; 38*4882a593Smuzhiyun dmas = <&dma 15 39*4882a593Smuzhiyun &dma 16>; 40*4882a593Smuzhiyun dma-names = "rx", "tx"; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun ssp2: ssp@41900000 { 44*4882a593Smuzhiyun compatibl3 = "mrvl,pxa3xx-ssp"; 45*4882a593Smuzhiyun reg = <0x41900000 0x40>; 46*4882a593Smuzhiyun ssp-id = <3>; 47*4882a593Smuzhiyun interrupts = <0>; 48*4882a593Smuzhiyun clock-names = "pxa27x-ssp.2"; 49*4882a593Smuzhiyun dmas = <&dma 66 50*4882a593Smuzhiyun &dma 67>; 51*4882a593Smuzhiyun dma-names = "rx", "tx"; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun ssp3: ssp@41a00000 { 55*4882a593Smuzhiyun compatible = "mrvl,pxa3xx-ssp"; 56*4882a593Smuzhiyun reg = <0x41a00000 0x40>; 57*4882a593Smuzhiyun ssp-id = <4>; 58*4882a593Smuzhiyun interrupts = <13>; 59*4882a593Smuzhiyun clock-names = "pxa27x-ssp.3"; 60*4882a593Smuzhiyun dmas = <&dma 2 61*4882a593Smuzhiyun &dma 3>; 62*4882a593Smuzhiyun dma-names = "rx", "tx"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65