1*4882a593Smuzhiyun* Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be "cirrus,ep7209-uart". 5*4882a593Smuzhiyun- reg: Address and length of the register set for the device. 6*4882a593Smuzhiyun- interrupts: Should contain UART TX and RX interrupt. 7*4882a593Smuzhiyun- clocks: Should contain UART core clock number. 8*4882a593Smuzhiyun- syscon: Phandle to SYSCON node, which contain UART control bits. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunOptional properties: 11*4882a593Smuzhiyun- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD 12*4882a593Smuzhiyun line respectively. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunNote: Each UART port should have an alias correctly numbered 15*4882a593Smuzhiyunin "aliases" node. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun aliases { 19*4882a593Smuzhiyun serial0 = &uart1; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun uart1: uart@80000480 { 23*4882a593Smuzhiyun compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart"; 24*4882a593Smuzhiyun reg = <0x80000480 0x80>; 25*4882a593Smuzhiyun interrupts = <12 13>; 26*4882a593Smuzhiyun clocks = <&clks 11>; 27*4882a593Smuzhiyun syscon = <&syscon1>; 28*4882a593Smuzhiyun cts-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>; 29*4882a593Smuzhiyun dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>; 30*4882a593Smuzhiyun dcd-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>; 31*4882a593Smuzhiyun }; 32