1*4882a593SmuzhiyunBinding for Cadence UART Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : 5*4882a593Smuzhiyun Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC. 6*4882a593Smuzhiyun Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC. 7*4882a593Smuzhiyun- reg: Should contain UART controller registers location and length. 8*4882a593Smuzhiyun- interrupts: Should contain UART controller interrupts. 9*4882a593Smuzhiyun- clocks: Must contain phandles to the UART clocks 10*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 11*4882a593Smuzhiyun- clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk" 12*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun- cts-override : Override the CTS modem status signal. This signal will 17*4882a593Smuzhiyun always be reported as active instead of being obtained from the modem status 18*4882a593Smuzhiyun register. Define this if your serial port does not use this pin 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun uart@e0000000 { 22*4882a593Smuzhiyun compatible = "cdns,uart-r1p8"; 23*4882a593Smuzhiyun clocks = <&clkc 23>, <&clkc 40>; 24*4882a593Smuzhiyun clock-names = "uart_clk", "pclk"; 25*4882a593Smuzhiyun reg = <0xE0000000 0x1000>; 26*4882a593Smuzhiyun interrupts = <0 27 4>; 27*4882a593Smuzhiyun }; 28