1*4882a593Smuzhiyun* BCM63xx UART 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: "brcm,bcm6345-uart" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun- reg: The base address of the UART register bank. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- interrupts: A single interrupt specifier. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- clocks: Clock driving the hardware; used to figure out the baud rate 12*4882a593Smuzhiyun divisor. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- clock-names: Should be "refclk". 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun uart0: serial@14e00520 { 22*4882a593Smuzhiyun compatible = "brcm,bcm6345-uart"; 23*4882a593Smuzhiyun reg = <0x14e00520 0x18>; 24*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 25*4882a593Smuzhiyun interrupts = <2>; 26*4882a593Smuzhiyun clocks = <&periph_clk>; 27*4882a593Smuzhiyun clock-names = "refclk"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clocks { 31*4882a593Smuzhiyun periph_clk: periph_clk@0 { 32*4882a593Smuzhiyun compatible = "fixed-clock"; 33*4882a593Smuzhiyun #clock-cells = <0>; 34*4882a593Smuzhiyun clock-frequency = <54000000>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37