1*4882a593Smuzhiyun* APM X-Gene Real Time Clock 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRTC controller for the APM X-Gene Real Time Clock 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun- compatible : Should be "apm,xgene-rtc" 7*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 8*4882a593Smuzhiyun region. 9*4882a593Smuzhiyun- interrupts: IRQ line for the RTC. 10*4882a593Smuzhiyun- #clock-cells: Should be 1. 11*4882a593Smuzhiyun- clocks: Reference to the clock entry. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample: 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunrtcclk: rtcclk { 16*4882a593Smuzhiyun compatible = "fixed-clock"; 17*4882a593Smuzhiyun #clock-cells = <1>; 18*4882a593Smuzhiyun clock-frequency = <100000000>; 19*4882a593Smuzhiyun clock-output-names = "rtcclk"; 20*4882a593Smuzhiyun}; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunrtc: rtc@10510000 { 23*4882a593Smuzhiyun compatible = "apm,xgene-rtc"; 24*4882a593Smuzhiyun reg = <0x0 0x10510000 0x0 0x400>; 25*4882a593Smuzhiyun interrupts = <0x0 0x46 0x4>; 26*4882a593Smuzhiyun #clock-cells = <1>; 27*4882a593Smuzhiyun clocks = <&rtcclk 0>; 28*4882a593Smuzhiyun}; 29