1*4882a593SmuzhiyunAtmel AT91SAM9260 Real Time Timer 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: should be one of the following: 5*4882a593Smuzhiyun - "atmel,at91sam9260-rtt" 6*4882a593Smuzhiyun - "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt" 7*4882a593Smuzhiyun- reg: should encode the memory region of the RTT controller 8*4882a593Smuzhiyun- interrupts: rtt alarm/event interrupt 9*4882a593Smuzhiyun- clocks: should contain the 32 KHz slow clk that will drive the RTT block. 10*4882a593Smuzhiyun- atmel,rtt-rtc-time-reg: should encode the GPBR register used to store 11*4882a593Smuzhiyun the time base when the RTT is used as an RTC. 12*4882a593Smuzhiyun The first cell should point to the GPBR node and the second one 13*4882a593Smuzhiyun encode the offset within the GPBR block (or in other words, the 14*4882a593Smuzhiyun GPBR register used to store the time base). 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunrtt@fffffd20 { 20*4882a593Smuzhiyun compatible = "atmel,at91sam9260-rtt"; 21*4882a593Smuzhiyun reg = <0xfffffd20 0x10>; 22*4882a593Smuzhiyun interrupts = <1 4 7>; 23*4882a593Smuzhiyun clocks = <&clk32k>; 24*4882a593Smuzhiyun atmel,rtt-rtc-time-reg = <&gpbr 0x0>; 25*4882a593Smuzhiyun}; 26