1*4882a593Smuzhiyun* Real Time Clock of the Armada 38x/7K/8K SoCs 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRTC controller for the Armada 38x, 7K and 8K SoCs 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun- compatible : Should be one of the following: 7*4882a593Smuzhiyun "marvell,armada-380-rtc" for Armada 38x SoC 8*4882a593Smuzhiyun "marvell,armada-8k-rtc" for Aramda 7K/8K SoCs 9*4882a593Smuzhiyun- reg: a list of base address and size pairs, one for each entry in 10*4882a593Smuzhiyun reg-names 11*4882a593Smuzhiyun- reg names: should contain: 12*4882a593Smuzhiyun * "rtc" for the RTC registers 13*4882a593Smuzhiyun * "rtc-soc" for the SoC related registers and among them the one 14*4882a593Smuzhiyun related to the interrupt. 15*4882a593Smuzhiyun- interrupts: IRQ line for the RTC. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunrtc@a3800 { 20*4882a593Smuzhiyun compatible = "marvell,armada-380-rtc"; 21*4882a593Smuzhiyun reg = <0xa3800 0x20>, <0x184a0 0x0c>; 22*4882a593Smuzhiyun reg-names = "rtc", "rtc-soc"; 23*4882a593Smuzhiyun interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 24*4882a593Smuzhiyun}; 25