1*4882a593SmuzhiyunRockchip SFC Controller for SOC 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "rockchip,sfc". 5*4882a593Smuzhiyun- reg : shall contain registers location and length for data and reg. 6*4882a593Smuzhiyun- interrupts : shall define the nand controller interrupt. 7*4882a593Smuzhiyun- clocks : shall reference sfc controller clocks. 8*4882a593Smuzhiyun- clock-names : sfc controller internal clock names. Shall contain : 9*4882a593Smuzhiyun * "clk_sfc" : sfc controller clock 10*4882a593Smuzhiyun * "hclk_sfc" : sfc ahb clock gate 11*4882a593Smuzhiyun- assigned-clocks : sclk preset by dts 12*4882a593Smuzhiyun- assigned-clock-frequency : sclk frequency, io clk = sclk/2; 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunExamples: 15*4882a593Smuzhiyunsfc: sfc@301c0000 { 16*4882a593Smuzhiyun compatible = "rockchip,sfc"; 17*4882a593Smuzhiyun reg = <0x301c0000 0x200>; 18*4882a593Smuzhiyun interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 19*4882a593Smuzhiyun clocks = <&clk_sfc>, <&clk_gates15 10>; 20*4882a593Smuzhiyun clock-names = "clk_sfc", "hclk_sfc"; 21*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_SFC>; 22*4882a593Smuzhiyun assigned-clock-frequency = <100000000>; 23*4882a593Smuzhiyun status = "okay"; 24*4882a593Smuzhiyun}; 25