1*4882a593SmuzhiyunRockchip NANDC Controller for SOC 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "rockchip,rk-nandc". 5*4882a593Smuzhiyun- reg : shall contain registers location and length for data and reg. 6*4882a593Smuzhiyun- interrupts : shall define the nandc controller interrupt. 7*4882a593Smuzhiyun- nandc_id : shall reference the number of nandc controllers; 8*4882a593Smuzhiyun- clocks : shall reference nandc controller clocks. 9*4882a593Smuzhiyun- clock-names : nandc controller internal clock names. Shall contain : 10*4882a593Smuzhiyun * "clk_nandc" : nand controller clock 11*4882a593Smuzhiyun * "hclk_nandc" : nandc ahb clock gate 12*4882a593Smuzhiyun * "g_clk_nandc" : nandc enable clock gate 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunExamples: 15*4882a593Smuzhiyunnandc: nandc@30100000 { 16*4882a593Smuzhiyun compatible = "rockchip,rk-nandc"; 17*4882a593Smuzhiyun reg = <0x0 0xff4b0000 0x0 0x4000>; 18*4882a593Smuzhiyun interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 19*4882a593Smuzhiyun nandc_id = <0>; 20*4882a593Smuzhiyun clocks = <&clk_nandc>, <&clk_gates15 3>, <&clk_gates5 3>; 21*4882a593Smuzhiyun clock-names = "clk_nandc", "hclk_nandc", "g_clk_nandc"; 22*4882a593Smuzhiyun status = "disabled"; 23*4882a593Smuzhiyun}; 24