1*4882a593SmuzhiyunBinding for the AXS10x reset controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding describes the ARC AXS10x boards custom IP-block which allows 4*4882a593Smuzhiyunto control reset signals of selected peripherals. For example DW GMAC, etc... 5*4882a593SmuzhiyunThis block is controlled via memory-mapped register (AKA CREG) which 6*4882a593Smuzhiyunrepresents up-to 32 reset lines. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunAs of today only the following lines are used: 9*4882a593Smuzhiyun - DW GMAC - line 5 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunThis binding uses the common reset binding[1]. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun[1] Documentation/devicetree/bindings/reset/reset.txt 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunRequired properties: 16*4882a593Smuzhiyun- compatible: should be "snps,axs10x-reset". 17*4882a593Smuzhiyun- reg: should always contain pair address - length: for creg reset 18*4882a593Smuzhiyun bits register. 19*4882a593Smuzhiyun- #reset-cells: from common reset binding; Should always be set to 1. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun reset: reset-controller@11220 { 23*4882a593Smuzhiyun compatible = "snps,axs10x-reset"; 24*4882a593Smuzhiyun #reset-cells = <1>; 25*4882a593Smuzhiyun reg = <0x11220 0x4>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunSpecifying reset lines connected to IP modules: 29*4882a593Smuzhiyun ethernet@.... { 30*4882a593Smuzhiyun .... 31*4882a593Smuzhiyun resets = <&reset 5>; 32*4882a593Smuzhiyun .... 33*4882a593Smuzhiyun }; 34