1*4882a593SmuzhiyunNXP LPC1850 Reset Generation Unit (RGU) 2*4882a593Smuzhiyun======================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunPlease also refer to reset.txt in this directory for common reset 5*4882a593Smuzhiyuncontroller binding usage. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: Should be "nxp,lpc1850-rgu" 9*4882a593Smuzhiyun- reg: register base and length 10*4882a593Smuzhiyun- clocks: phandle and clock specifier to RGU clocks 11*4882a593Smuzhiyun- clock-names: should contain "delay" and "reg" 12*4882a593Smuzhiyun- #reset-cells: should be 1 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunSee table below for valid peripheral reset numbers. Numbers not 15*4882a593Smuzhiyunin the table below are either reserved or not applicable for 16*4882a593Smuzhiyunnormal operation. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunReset Peripheral 19*4882a593Smuzhiyun 9 System control unit (SCU) 20*4882a593Smuzhiyun 12 ARM Cortex-M0 subsystem core (LPC43xx only) 21*4882a593Smuzhiyun 13 CPU core 22*4882a593Smuzhiyun 16 LCD controller 23*4882a593Smuzhiyun 17 USB0 24*4882a593Smuzhiyun 18 USB1 25*4882a593Smuzhiyun 19 DMA 26*4882a593Smuzhiyun 20 SDIO 27*4882a593Smuzhiyun 21 External memory controller (EMC) 28*4882a593Smuzhiyun 22 Ethernet 29*4882a593Smuzhiyun 25 Flash bank A 30*4882a593Smuzhiyun 27 EEPROM 31*4882a593Smuzhiyun 28 GPIO 32*4882a593Smuzhiyun 29 Flash bank B 33*4882a593Smuzhiyun 32 Timer0 34*4882a593Smuzhiyun 33 Timer1 35*4882a593Smuzhiyun 34 Timer2 36*4882a593Smuzhiyun 35 Timer3 37*4882a593Smuzhiyun 36 Repetitive Interrupt timer (RIT) 38*4882a593Smuzhiyun 37 State Configurable Timer (SCT) 39*4882a593Smuzhiyun 38 Motor control PWM (MCPWM) 40*4882a593Smuzhiyun 39 QEI 41*4882a593Smuzhiyun 40 ADC0 42*4882a593Smuzhiyun 41 ADC1 43*4882a593Smuzhiyun 42 DAC 44*4882a593Smuzhiyun 44 USART0 45*4882a593Smuzhiyun 45 UART1 46*4882a593Smuzhiyun 46 USART2 47*4882a593Smuzhiyun 47 USART3 48*4882a593Smuzhiyun 48 I2C0 49*4882a593Smuzhiyun 49 I2C1 50*4882a593Smuzhiyun 50 SSP0 51*4882a593Smuzhiyun 51 SSP1 52*4882a593Smuzhiyun 52 I2S0 and I2S1 53*4882a593Smuzhiyun 53 Serial Flash Interface (SPIFI) 54*4882a593Smuzhiyun 54 C_CAN1 55*4882a593Smuzhiyun 55 C_CAN0 56*4882a593Smuzhiyun 56 ARM Cortex-M0 application core (LPC4370 only) 57*4882a593Smuzhiyun 57 SGPIO (LPC43xx only) 58*4882a593Smuzhiyun 58 SPI (LPC43xx only) 59*4882a593Smuzhiyun 60 ADCHS (12-bit ADC) (LPC4370 only) 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunRefer to NXP LPC18xx or LPC43xx user manual for more details about 62*4882a593Smuzhiyunthe reset signals and the connected block/peripheral. 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunReset provider example: 65*4882a593Smuzhiyunrgu: reset-controller@40053000 { 66*4882a593Smuzhiyun compatible = "nxp,lpc1850-rgu"; 67*4882a593Smuzhiyun reg = <0x40053000 0x1000>; 68*4882a593Smuzhiyun clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; 69*4882a593Smuzhiyun clock-names = "delay", "reg"; 70*4882a593Smuzhiyun #reset-cells = <1>; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunReset consumer example: 74*4882a593Smuzhiyunmac: ethernet@40010000 { 75*4882a593Smuzhiyun compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; 76*4882a593Smuzhiyun reg = <0x40010000 0x2000>; 77*4882a593Smuzhiyun interrupts = <5>; 78*4882a593Smuzhiyun interrupt-names = "macirq"; 79*4882a593Smuzhiyun clocks = <&ccu1 CLK_CPU_ETHERNET>; 80*4882a593Smuzhiyun clock-names = "stmmaceth"; 81*4882a593Smuzhiyun resets = <&rgu 22>; 82*4882a593Smuzhiyun reset-names = "stmmaceth"; 83*4882a593Smuzhiyun}; 84