1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: System Reset Controller on Intel Gateway SoCs 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Dilip Kota <eswara.kota@linux.intel.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun enum: 15*4882a593Smuzhiyun - intel,rcu-lgm 16*4882a593Smuzhiyun - intel,rcu-xrx200 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun reg: 19*4882a593Smuzhiyun description: Reset controller registers. 20*4882a593Smuzhiyun maxItems: 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun intel,global-reset: 23*4882a593Smuzhiyun description: Global reset register offset and bit offset. 24*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32-array 25*4882a593Smuzhiyun items: 26*4882a593Smuzhiyun - description: Register offset 27*4882a593Smuzhiyun - description: Register bit offset 28*4882a593Smuzhiyun minimum: 0 29*4882a593Smuzhiyun maximum: 31 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun "#reset-cells": 32*4882a593Smuzhiyun minimum: 2 33*4882a593Smuzhiyun maximum: 3 34*4882a593Smuzhiyun description: | 35*4882a593Smuzhiyun First cell is reset request register offset. 36*4882a593Smuzhiyun Second cell is bit offset in reset request register. 37*4882a593Smuzhiyun Third cell is bit offset in reset status register. 38*4882a593Smuzhiyun For LGM SoC, reset cell count is 2 as bit offset in 39*4882a593Smuzhiyun reset request and reset status registers is same. Whereas 40*4882a593Smuzhiyun 3 for legacy SoCs as bit offset differs. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunrequired: 43*4882a593Smuzhiyun - compatible 44*4882a593Smuzhiyun - reg 45*4882a593Smuzhiyun - intel,global-reset 46*4882a593Smuzhiyun - "#reset-cells" 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunadditionalProperties: false 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunexamples: 51*4882a593Smuzhiyun - | 52*4882a593Smuzhiyun rcu0: reset-controller@e0000000 { 53*4882a593Smuzhiyun compatible = "intel,rcu-lgm"; 54*4882a593Smuzhiyun reg = <0xe0000000 0x20000>; 55*4882a593Smuzhiyun intel,global-reset = <0x10 30>; 56*4882a593Smuzhiyun #reset-cells = <2>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun pwm: pwm@e0d00000 { 60*4882a593Smuzhiyun status = "disabled"; 61*4882a593Smuzhiyun compatible = "intel,lgm-pwm"; 62*4882a593Smuzhiyun reg = <0xe0d00000 0x30>; 63*4882a593Smuzhiyun clocks = <&cgu0 1>; 64*4882a593Smuzhiyun #pwm-cells = <2>; 65*4882a593Smuzhiyun resets = <&rcu0 0x30 21>; 66*4882a593Smuzhiyun }; 67