1*4882a593SmuzhiyunPistachio Reset Controller 2*4882a593Smuzhiyun============================================================================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThis binding describes a reset controller device that is used to enable and 5*4882a593Smuzhiyundisable individual IP blocks within the Pistachio SoC using "soft reset" 6*4882a593Smuzhiyuncontrol bits found in the Pistachio SoC top level registers. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunThe actual action taken when soft reset is asserted is hardware dependent. 9*4882a593SmuzhiyunHowever, when asserted it may not be possible to access the hardware's 10*4882a593Smuzhiyunregisters, and following an assert/deassert sequence the hardware's previous 11*4882a593Smuzhiyunstate may no longer be valid. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunPlease refer to Documentation/devicetree/bindings/reset/reset.txt 14*4882a593Smuzhiyunfor common reset controller binding usage. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRequired properties: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- compatible: Contains "img,pistachio-reset" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- #reset-cells: Contains 1 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun cr_periph: clk@18148000 { 25*4882a593Smuzhiyun compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd"; 26*4882a593Smuzhiyun reg = <0x18148000 0x1000>; 27*4882a593Smuzhiyun clocks = <&clk_periph PERIPH_CLK_SYS>; 28*4882a593Smuzhiyun clock-names = "sys"; 29*4882a593Smuzhiyun #clock-cells = <1>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun pistachio_reset: reset-controller { 32*4882a593Smuzhiyun compatible = "img,pistachio-reset"; 33*4882a593Smuzhiyun #reset-cells = <1>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunSpecifying reset control of devices 38*4882a593Smuzhiyun======================================= 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunDevice nodes should specify the reset channel required in their "resets" 41*4882a593Smuzhiyunproperty, containing a phandle to the pistachio reset device node and an 42*4882a593Smuzhiyunindex specifying which reset to use, as described in 43*4882a593SmuzhiyunDocumentation/devicetree/bindings/reset/reset.txt. 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunExample: 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun spdif_out: spdif-out@18100d00 { 48*4882a593Smuzhiyun ... 49*4882a593Smuzhiyun resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>; 50*4882a593Smuzhiyun reset-names = "rst"; 51*4882a593Smuzhiyun ... 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunMacro definitions for the supported resets can be found in: 55*4882a593Smuzhiyuninclude/dt-bindings/reset/pistachio-resets.h 56