1*4882a593SmuzhiyunHisilicon System Reset Controller 2*4882a593Smuzhiyun====================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunPlease also refer to reset.txt in this directory for common reset 5*4882a593Smuzhiyuncontroller binding usage. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThe reset controller registers are part of the system-ctl block on 8*4882a593Smuzhiyunhi6220 SoC. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible: should be one of the following: 12*4882a593Smuzhiyun - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller. 13*4882a593Smuzhiyun - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller. 14*4882a593Smuzhiyun - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller. 15*4882a593Smuzhiyun- reg: should be register base and length as documented in the 16*4882a593Smuzhiyun datasheet 17*4882a593Smuzhiyun- #reset-cells: 1, see below 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: 20*4882a593Smuzhiyunsys_ctrl: sys_ctrl@f7030000 { 21*4882a593Smuzhiyun compatible = "hisilicon,hi6220-sysctrl", "syscon"; 22*4882a593Smuzhiyun reg = <0x0 0xf7030000 0x0 0x2000>; 23*4882a593Smuzhiyun #clock-cells = <1>; 24*4882a593Smuzhiyun #reset-cells = <1>; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunSpecifying reset lines connected to IP modules 28*4882a593Smuzhiyun============================================== 29*4882a593Smuzhiyunexample: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun uart1: serial@..... { 32*4882a593Smuzhiyun ... 33*4882a593Smuzhiyun resets = <&sys_ctrl PERIPH_RSTEN3_UART1>; 34*4882a593Smuzhiyun ... 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunThe index could be found in <dt-bindings/reset/hisi,hi6220-resets.h>. 38