1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/reset/fsl,imx-src.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale i.MX System Reset Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Philipp Zabel <p.zabel@pengutronix.de> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The system reset controller can be used to reset the GPU, VPU, 14*4882a593Smuzhiyun IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device 15*4882a593Smuzhiyun nodes should specify the reset line on the SRC in their resets 16*4882a593Smuzhiyun property, containing a phandle to the SRC device node and a 17*4882a593Smuzhiyun RESET_INDEX specifying which module to reset, as described in 18*4882a593Smuzhiyun reset.txt 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun The following RESET_INDEX values are valid for i.MX5: 21*4882a593Smuzhiyun GPU_RESET 0 22*4882a593Smuzhiyun VPU_RESET 1 23*4882a593Smuzhiyun IPU1_RESET 2 24*4882a593Smuzhiyun OPEN_VG_RESET 3 25*4882a593Smuzhiyun The following additional RESET_INDEX value is valid for i.MX6: 26*4882a593Smuzhiyun IPU2_RESET 4 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunproperties: 29*4882a593Smuzhiyun compatible: 30*4882a593Smuzhiyun oneOf: 31*4882a593Smuzhiyun - const: "fsl,imx51-src" 32*4882a593Smuzhiyun - items: 33*4882a593Smuzhiyun - const: "fsl,imx50-src" 34*4882a593Smuzhiyun - const: "fsl,imx51-src" 35*4882a593Smuzhiyun - items: 36*4882a593Smuzhiyun - const: "fsl,imx53-src" 37*4882a593Smuzhiyun - const: "fsl,imx51-src" 38*4882a593Smuzhiyun - items: 39*4882a593Smuzhiyun - const: "fsl,imx6q-src" 40*4882a593Smuzhiyun - const: "fsl,imx51-src" 41*4882a593Smuzhiyun - items: 42*4882a593Smuzhiyun - const: "fsl,imx6sx-src" 43*4882a593Smuzhiyun - const: "fsl,imx51-src" 44*4882a593Smuzhiyun - items: 45*4882a593Smuzhiyun - const: "fsl,imx6sl-src" 46*4882a593Smuzhiyun - const: "fsl,imx51-src" 47*4882a593Smuzhiyun - items: 48*4882a593Smuzhiyun - const: "fsl,imx6ul-src" 49*4882a593Smuzhiyun - const: "fsl,imx51-src" 50*4882a593Smuzhiyun - items: 51*4882a593Smuzhiyun - const: "fsl,imx6sll-src" 52*4882a593Smuzhiyun - const: "fsl,imx51-src" 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun reg: 55*4882a593Smuzhiyun maxItems: 1 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun interrupts: 58*4882a593Smuzhiyun items: 59*4882a593Smuzhiyun - description: SRC interrupt 60*4882a593Smuzhiyun - description: CPU WDOG interrupts out of SRC 61*4882a593Smuzhiyun minItems: 1 62*4882a593Smuzhiyun maxItems: 2 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun '#reset-cells': 65*4882a593Smuzhiyun const: 1 66*4882a593Smuzhiyun 67*4882a593Smuzhiyunrequired: 68*4882a593Smuzhiyun - compatible 69*4882a593Smuzhiyun - reg 70*4882a593Smuzhiyun - interrupts 71*4882a593Smuzhiyun - '#reset-cells' 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunadditionalProperties: false 74*4882a593Smuzhiyun 75*4882a593Smuzhiyunexamples: 76*4882a593Smuzhiyun - | 77*4882a593Smuzhiyun reset-controller@73fd0000 { 78*4882a593Smuzhiyun compatible = "fsl,imx51-src"; 79*4882a593Smuzhiyun reg = <0x73fd0000 0x4000>; 80*4882a593Smuzhiyun interrupts = <75>; 81*4882a593Smuzhiyun #reset-cells = <1>; 82*4882a593Smuzhiyun }; 83