1*4882a593SmuzhiyunBroadcom STB SW_INIT-style reset controller 2*4882a593Smuzhiyun=========================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunBroadcom STB SoCs have a SW_INIT-style reset controller with separate 5*4882a593SmuzhiyunSET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit 6*4882a593Smuzhiyunreset lines. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunPlease also refer to reset.txt in this directory for common reset 9*4882a593Smuzhiyuncontroller binding usage. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties: 12*4882a593Smuzhiyun- compatible: should be brcm,brcmstb-reset 13*4882a593Smuzhiyun- reg: register base and length 14*4882a593Smuzhiyun- #reset-cells: must be set to 1 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun reset: reset-controller@8404318 { 19*4882a593Smuzhiyun compatible = "brcm,brcmstb-reset"; 20*4882a593Smuzhiyun reg = <0x8404318 0x30>; 21*4882a593Smuzhiyun #reset-cells = <1>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun ðernet_switch { 25*4882a593Smuzhiyun resets = <&reset 26>; 26*4882a593Smuzhiyun reset-names = "switch"; 27*4882a593Smuzhiyun }; 28