1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner A31 Peripheral Reset Controller Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundeprecated: true
14*4882a593Smuzhiyun
15*4882a593Smuzhiyunselect:
16*4882a593Smuzhiyun  properties:
17*4882a593Smuzhiyun    compatible:
18*4882a593Smuzhiyun      contains:
19*4882a593Smuzhiyun        enum:
20*4882a593Smuzhiyun          - allwinner,sun6i-a31-ahb1-reset
21*4882a593Smuzhiyun          - allwinner,sun6i-a31-clock-reset
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun  # The PRCM on the A31 and A23 will have the reg property missing,
24*4882a593Smuzhiyun  # since it's set at the upper level node, and will be validated by
25*4882a593Smuzhiyun  # PRCM's schema. Make sure we only validate standalone nodes.
26*4882a593Smuzhiyun  required:
27*4882a593Smuzhiyun    - compatible
28*4882a593Smuzhiyun    - reg
29*4882a593Smuzhiyun
30*4882a593Smuzhiyunproperties:
31*4882a593Smuzhiyun  "#reset-cells":
32*4882a593Smuzhiyun    const: 1
33*4882a593Smuzhiyun    description: >
34*4882a593Smuzhiyun      This additional argument passed to that reset controller is the
35*4882a593Smuzhiyun      offset of the bit controlling this particular reset line in the
36*4882a593Smuzhiyun      register.
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun  compatible:
39*4882a593Smuzhiyun    enum:
40*4882a593Smuzhiyun      - allwinner,sun6i-a31-ahb1-reset
41*4882a593Smuzhiyun      - allwinner,sun6i-a31-clock-reset
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun  reg:
44*4882a593Smuzhiyun    maxItems: 1
45*4882a593Smuzhiyun
46*4882a593Smuzhiyunrequired:
47*4882a593Smuzhiyun  - "#reset-cells"
48*4882a593Smuzhiyun  - compatible
49*4882a593Smuzhiyun  - reg
50*4882a593Smuzhiyun
51*4882a593SmuzhiyunadditionalProperties: false
52*4882a593Smuzhiyun
53*4882a593Smuzhiyunexamples:
54*4882a593Smuzhiyun  - |
55*4882a593Smuzhiyun    ahb1_rst: reset@1c202c0 {
56*4882a593Smuzhiyun        #reset-cells = <1>;
57*4882a593Smuzhiyun        compatible = "allwinner,sun6i-a31-ahb1-reset";
58*4882a593Smuzhiyun        reg = <0x01c202c0 0xc>;
59*4882a593Smuzhiyun    };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun  - |
62*4882a593Smuzhiyun    apbs_rst: reset@80014b0 {
63*4882a593Smuzhiyun        #reset-cells = <1>;
64*4882a593Smuzhiyun        compatible = "allwinner,sun6i-a31-clock-reset";
65*4882a593Smuzhiyun        reg = <0x080014b0 0x4>;
66*4882a593Smuzhiyun    };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun...
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