1*4882a593SmuzhiyunTWL family of regulators 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593SmuzhiyunFor twl6030 regulators/LDOs 5*4882a593Smuzhiyun- compatible: 6*4882a593Smuzhiyun - "ti,twl6030-vaux1" for VAUX1 LDO 7*4882a593Smuzhiyun - "ti,twl6030-vaux2" for VAUX2 LDO 8*4882a593Smuzhiyun - "ti,twl6030-vaux3" for VAUX3 LDO 9*4882a593Smuzhiyun - "ti,twl6030-vmmc" for VMMC LDO 10*4882a593Smuzhiyun - "ti,twl6030-vpp" for VPP LDO 11*4882a593Smuzhiyun - "ti,twl6030-vusim" for VUSIM LDO 12*4882a593Smuzhiyun - "ti,twl6030-vana" for VANA LDO 13*4882a593Smuzhiyun - "ti,twl6030-vcxio" for VCXIO LDO 14*4882a593Smuzhiyun - "ti,twl6030-vdac" for VDAC LDO 15*4882a593Smuzhiyun - "ti,twl6030-vusb" for VUSB LDO 16*4882a593Smuzhiyun - "ti,twl6030-v1v8" for V1V8 LDO 17*4882a593Smuzhiyun - "ti,twl6030-v2v1" for V2V1 LDO 18*4882a593Smuzhiyun - "ti,twl6030-vdd1" for VDD1 SMPS 19*4882a593Smuzhiyun - "ti,twl6030-vdd2" for VDD2 SMPS 20*4882a593Smuzhiyun - "ti,twl6030-vdd3" for VDD3 SMPS 21*4882a593SmuzhiyunFor twl6032 regulators/LDOs 22*4882a593Smuzhiyun- compatible: 23*4882a593Smuzhiyun - "ti,twl6032-ldo1" for LDO1 LDO 24*4882a593Smuzhiyun - "ti,twl6032-ldo2" for LDO2 LDO 25*4882a593Smuzhiyun - "ti,twl6032-ldo3" for LDO3 LDO 26*4882a593Smuzhiyun - "ti,twl6032-ldo4" for LDO4 LDO 27*4882a593Smuzhiyun - "ti,twl6032-ldo5" for LDO5 LDO 28*4882a593Smuzhiyun - "ti,twl6032-ldo6" for LDO6 LDO 29*4882a593Smuzhiyun - "ti,twl6032-ldo7" for LDO7 LDO 30*4882a593Smuzhiyun - "ti,twl6032-ldoln" for LDOLN LDO 31*4882a593Smuzhiyun - "ti,twl6032-ldousb" for LDOUSB LDO 32*4882a593Smuzhiyun - "ti,twl6032-smps3" for SMPS3 SMPS 33*4882a593Smuzhiyun - "ti,twl6032-smps4" for SMPS4 SMPS 34*4882a593Smuzhiyun - "ti,twl6032-vio" for VIO SMPS 35*4882a593SmuzhiyunFor twl4030 regulators/LDOs 36*4882a593Smuzhiyun- compatible: 37*4882a593Smuzhiyun - "ti,twl4030-vaux1" for VAUX1 LDO 38*4882a593Smuzhiyun - "ti,twl4030-vaux2" for VAUX2 LDO 39*4882a593Smuzhiyun - "ti,twl5030-vaux2" for VAUX2 LDO 40*4882a593Smuzhiyun - "ti,twl4030-vaux3" for VAUX3 LDO 41*4882a593Smuzhiyun - "ti,twl4030-vaux4" for VAUX4 LDO 42*4882a593Smuzhiyun - "ti,twl4030-vmmc1" for VMMC1 LDO 43*4882a593Smuzhiyun - "ti,twl4030-vmmc2" for VMMC2 LDO 44*4882a593Smuzhiyun - "ti,twl4030-vpll1" for VPLL1 LDO 45*4882a593Smuzhiyun - "ti,twl4030-vpll2" for VPLL2 LDO 46*4882a593Smuzhiyun - "ti,twl4030-vsim" for VSIM LDO 47*4882a593Smuzhiyun - "ti,twl4030-vdac" for VDAC LDO 48*4882a593Smuzhiyun - "ti,twl4030-vintana2" for VINTANA2 LDO 49*4882a593Smuzhiyun - "ti,twl4030-vio" for VIO LDO 50*4882a593Smuzhiyun - "ti,twl4030-vdd1" for VDD1 SMPS 51*4882a593Smuzhiyun - "ti,twl4030-vdd2" for VDD2 SMPS 52*4882a593Smuzhiyun - "ti,twl4030-vintana1" for VINTANA1 LDO 53*4882a593Smuzhiyun - "ti,twl4030-vintdig" for VINTDIG LDO 54*4882a593Smuzhiyun - "ti,twl4030-vusb1v5" for VUSB1V5 LDO 55*4882a593Smuzhiyun - "ti,twl4030-vusb1v8" for VUSB1V8 LDO 56*4882a593Smuzhiyun - "ti,twl4030-vusb3v1" for VUSB3V1 LDO 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunOptional properties: 59*4882a593Smuzhiyun- Any optional property defined in bindings/regulator/regulator.txt 60*4882a593SmuzhiyunFor twl4030 regulators/LDOs: 61*4882a593Smuzhiyun - regulator-initial-mode: 62*4882a593Smuzhiyun - 0x08 - Sleep mode, the nominal output voltage is maintained with low power 63*4882a593Smuzhiyun consumption with low load current capability. 64*4882a593Smuzhiyun - 0x0e - Active mode, the regulator can deliver its nominal output voltage 65*4882a593Smuzhiyun with full-load current capability. 66*4882a593Smuzhiyun 67*4882a593SmuzhiyunExample: 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun xyz: regulator@0 { 70*4882a593Smuzhiyun compatible = "ti,twl6030-vaux1"; 71*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 72*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunFor twl6030 regulators/LDOs: 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun - ti,retain-on-reset: Does not turn off the supplies during warm 78*4882a593Smuzhiyun reset. Could be needed for VMMC, as TWL6030 79*4882a593Smuzhiyun reset sequence for this signal does not comply 80*4882a593Smuzhiyun with the SD specification. 81