1*4882a593SmuzhiyunVIA/Wondermedia VT8500/WM8xxx series SoC PWM controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: should be "via,vt8500-pwm" 5*4882a593Smuzhiyun- reg: physical base address and length of the controller's registers 6*4882a593Smuzhiyun- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of 7*4882a593Smuzhiyun the cells format. The only third cell flag supported by this binding is 8*4882a593Smuzhiyun PWM_POLARITY_INVERTED. 9*4882a593Smuzhiyun- clocks: phandle to the PWM source clock 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunExample: 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunpwm1: pwm@d8220000 { 14*4882a593Smuzhiyun #pwm-cells = <3>; 15*4882a593Smuzhiyun compatible = "via,vt8500-pwm"; 16*4882a593Smuzhiyun reg = <0xd8220000 0x1000>; 17*4882a593Smuzhiyun clocks = <&clkpwm>; 18*4882a593Smuzhiyun}; 19