1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pwm/renesas,tpu-pwm.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Renesas R-Car Timer Pulse Unit PWM Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun items: 15*4882a593Smuzhiyun - enum: 16*4882a593Smuzhiyun - renesas,tpu-r8a73a4 # R-Mobile APE6 17*4882a593Smuzhiyun - renesas,tpu-r8a7740 # R-Mobile A1 18*4882a593Smuzhiyun - renesas,tpu-r8a7742 # RZ/G1H 19*4882a593Smuzhiyun - renesas,tpu-r8a7743 # RZ/G1M 20*4882a593Smuzhiyun - renesas,tpu-r8a7744 # RZ/G1N 21*4882a593Smuzhiyun - renesas,tpu-r8a7745 # RZ/G1E 22*4882a593Smuzhiyun - renesas,tpu-r8a7790 # R-Car H2 23*4882a593Smuzhiyun - renesas,tpu-r8a7791 # R-Car M2-W 24*4882a593Smuzhiyun - renesas,tpu-r8a7792 # R-Car V2H 25*4882a593Smuzhiyun - renesas,tpu-r8a7793 # R-Car M2-N 26*4882a593Smuzhiyun - renesas,tpu-r8a7794 # R-Car E2 27*4882a593Smuzhiyun - renesas,tpu-r8a7795 # R-Car H3 28*4882a593Smuzhiyun - renesas,tpu-r8a7796 # R-Car M3-W 29*4882a593Smuzhiyun - renesas,tpu-r8a77965 # R-Car M3-N 30*4882a593Smuzhiyun - renesas,tpu-r8a77970 # R-Car V3M 31*4882a593Smuzhiyun - renesas,tpu-r8a77980 # R-Car V3H 32*4882a593Smuzhiyun - const: renesas,tpu 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun reg: 35*4882a593Smuzhiyun # Base address and length of each memory resource used by the PWM 36*4882a593Smuzhiyun # controller hardware module. 37*4882a593Smuzhiyun maxItems: 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun interrupts: 40*4882a593Smuzhiyun maxItems: 1 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun '#pwm-cells': 43*4882a593Smuzhiyun # should be 3. See pwm.yaml in this directory for a description of 44*4882a593Smuzhiyun # the cells format. The only third cell flag supported by this binding is 45*4882a593Smuzhiyun # PWM_POLARITY_INVERTED. 46*4882a593Smuzhiyun const: 3 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun clocks: 49*4882a593Smuzhiyun maxItems: 1 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun power-domains: 52*4882a593Smuzhiyun maxItems: 1 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun resets: 55*4882a593Smuzhiyun maxItems: 1 56*4882a593Smuzhiyun 57*4882a593Smuzhiyunrequired: 58*4882a593Smuzhiyun - compatible 59*4882a593Smuzhiyun - reg 60*4882a593Smuzhiyun - '#pwm-cells' 61*4882a593Smuzhiyun 62*4882a593SmuzhiyunadditionalProperties: false 63*4882a593Smuzhiyun 64*4882a593Smuzhiyunexamples: 65*4882a593Smuzhiyun - | 66*4882a593Smuzhiyun #include <dt-bindings/clock/r8a7740-clock.h> 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun tpu: pwm@e6600000 { 69*4882a593Smuzhiyun compatible = "renesas,tpu-r8a7740", "renesas,tpu"; 70*4882a593Smuzhiyun reg = <0xe6600000 0x148>; 71*4882a593Smuzhiyun clocks = <&mstp3_clks R8A7740_CLK_TPU0>; 72*4882a593Smuzhiyun power-domains = <&pd_a3sp>; 73*4882a593Smuzhiyun #pwm-cells = <3>; 74*4882a593Smuzhiyun }; 75