1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Renesas R-Car PWM Timer Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun items: 15*4882a593Smuzhiyun - enum: 16*4882a593Smuzhiyun - renesas,pwm-r8a7742 # RZ/G1H 17*4882a593Smuzhiyun - renesas,pwm-r8a7743 # RZ/G1M 18*4882a593Smuzhiyun - renesas,pwm-r8a7744 # RZ/G1N 19*4882a593Smuzhiyun - renesas,pwm-r8a7745 # RZ/G1E 20*4882a593Smuzhiyun - renesas,pwm-r8a77470 # RZ/G1C 21*4882a593Smuzhiyun - renesas,pwm-r8a774a1 # RZ/G2M 22*4882a593Smuzhiyun - renesas,pwm-r8a774b1 # RZ/G2N 23*4882a593Smuzhiyun - renesas,pwm-r8a774c0 # RZ/G2E 24*4882a593Smuzhiyun - renesas,pwm-r8a774e1 # RZ/G2H 25*4882a593Smuzhiyun - renesas,pwm-r8a7778 # R-Car M1A 26*4882a593Smuzhiyun - renesas,pwm-r8a7779 # R-Car H1 27*4882a593Smuzhiyun - renesas,pwm-r8a7790 # R-Car H2 28*4882a593Smuzhiyun - renesas,pwm-r8a7791 # R-Car M2-W 29*4882a593Smuzhiyun - renesas,pwm-r8a7794 # R-Car E2 30*4882a593Smuzhiyun - renesas,pwm-r8a7795 # R-Car H3 31*4882a593Smuzhiyun - renesas,pwm-r8a7796 # R-Car M3-W 32*4882a593Smuzhiyun - renesas,pwm-r8a77961 # R-Car M3-W+ 33*4882a593Smuzhiyun - renesas,pwm-r8a77965 # R-Car M3-N 34*4882a593Smuzhiyun - renesas,pwm-r8a77970 # R-Car V3M 35*4882a593Smuzhiyun - renesas,pwm-r8a77980 # R-Car V3H 36*4882a593Smuzhiyun - renesas,pwm-r8a77990 # R-Car E3 37*4882a593Smuzhiyun - renesas,pwm-r8a77995 # R-Car D3 38*4882a593Smuzhiyun - const: renesas,pwm-rcar 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun reg: 41*4882a593Smuzhiyun # base address and length of the registers block for the PWM. 42*4882a593Smuzhiyun maxItems: 1 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun '#pwm-cells': 45*4882a593Smuzhiyun # should be 2. See pwm.yaml in this directory for a description of 46*4882a593Smuzhiyun # the cells format. 47*4882a593Smuzhiyun const: 2 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun clocks: 50*4882a593Smuzhiyun # clock phandle and specifier pair. 51*4882a593Smuzhiyun maxItems: 1 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun power-domains: 54*4882a593Smuzhiyun maxItems: 1 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun resets: 57*4882a593Smuzhiyun maxItems: 1 58*4882a593Smuzhiyun 59*4882a593Smuzhiyunrequired: 60*4882a593Smuzhiyun - compatible 61*4882a593Smuzhiyun - reg 62*4882a593Smuzhiyun - '#pwm-cells' 63*4882a593Smuzhiyun - clocks 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunadditionalProperties: false 66*4882a593Smuzhiyun 67*4882a593Smuzhiyunexamples: 68*4882a593Smuzhiyun - | 69*4882a593Smuzhiyun #include <dt-bindings/clock/r8a7743-cpg-mssr.h> 70*4882a593Smuzhiyun #include <dt-bindings/power/r8a7743-sysc.h> 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun pwm0: pwm@e6e30000 { 73*4882a593Smuzhiyun compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; 74*4882a593Smuzhiyun reg = <0xe6e30000 0x8>; 75*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 523>; 76*4882a593Smuzhiyun power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; 77*4882a593Smuzhiyun resets = <&cpg 523>; 78*4882a593Smuzhiyun #pwm-cells = <2>; 79*4882a593Smuzhiyun pinctrl-0 = <&pwm0_pins>; 80*4882a593Smuzhiyun pinctrl-names = "default"; 81*4882a593Smuzhiyun }; 82