xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pwm/pwm-zx.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593SmuzhiyunZTE ZX PWM controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties:
4*4882a593Smuzhiyun - compatible: Should be "zte,zx296718-pwm".
5*4882a593Smuzhiyun - reg: Physical base address and length of the controller's registers.
6*4882a593Smuzhiyun - clocks : The phandle and specifier referencing the controller's clocks.
7*4882a593Smuzhiyun - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller.  The
8*4882a593Smuzhiyun   PCLK is for register access, while WCLK is the reference clock for
9*4882a593Smuzhiyun   calculating period and duty cycles.
10*4882a593Smuzhiyun - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
11*4882a593Smuzhiyun   the cells format.
12*4882a593Smuzhiyun
13*4882a593SmuzhiyunExample:
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	pwm: pwm@1439000 {
16*4882a593Smuzhiyun		compatible = "zte,zx296718-pwm";
17*4882a593Smuzhiyun		reg = <0x1439000 0x1000>;
18*4882a593Smuzhiyun		clocks = <&lsp1crm LSP1_PWM_PCLK>,
19*4882a593Smuzhiyun			 <&lsp1crm LSP1_PWM_WCLK>;
20*4882a593Smuzhiyun		clock-names = "pclk", "wclk";
21*4882a593Smuzhiyun		#pwm-cells = <3>;
22*4882a593Smuzhiyun	};
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