1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright (C) 2020 SiFive, Inc. 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml# 6*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: SiFive PWM controller 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Yash Shah <yash.shah@sifive.com> 12*4882a593Smuzhiyun - Sagar Kadam <sagar.kadam@sifive.com> 13*4882a593Smuzhiyun - Paul Walmsley <paul.walmsley@sifive.com> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyundescription: 16*4882a593Smuzhiyun Unlike most other PWM controllers, the SiFive PWM controller currently 17*4882a593Smuzhiyun only supports one period for all channels in the PWM. All PWMs need to 18*4882a593Smuzhiyun run at the same period. The period also has significant restrictions on 19*4882a593Smuzhiyun the values it can achieve, which the driver rounds to the nearest 20*4882a593Smuzhiyun achievable period. PWM RTL that corresponds to the IP block version 21*4882a593Smuzhiyun numbers can be found here - 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunproperties: 26*4882a593Smuzhiyun compatible: 27*4882a593Smuzhiyun items: 28*4882a593Smuzhiyun - const: sifive,fu540-c000-pwm 29*4882a593Smuzhiyun - const: sifive,pwm0 30*4882a593Smuzhiyun description: 31*4882a593Smuzhiyun Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported 32*4882a593Smuzhiyun compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0 33*4882a593Smuzhiyun as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the 34*4882a593Smuzhiyun SiFive PWM v0 IP block with no chip integration tweaks. 35*4882a593Smuzhiyun Please refer to sifive-blocks-ip-versioning.txt for details. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun reg: 38*4882a593Smuzhiyun maxItems: 1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun clocks: 41*4882a593Smuzhiyun maxItems: 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun "#pwm-cells": 44*4882a593Smuzhiyun const: 3 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun interrupts: 47*4882a593Smuzhiyun maxItems: 4 48*4882a593Smuzhiyun description: 49*4882a593Smuzhiyun Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator. 50*4882a593Smuzhiyun 51*4882a593Smuzhiyunrequired: 52*4882a593Smuzhiyun - compatible 53*4882a593Smuzhiyun - reg 54*4882a593Smuzhiyun - clocks 55*4882a593Smuzhiyun - "#pwm-cells" 56*4882a593Smuzhiyun - interrupts 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunadditionalProperties: false 59*4882a593Smuzhiyun 60*4882a593Smuzhiyunexamples: 61*4882a593Smuzhiyun - | 62*4882a593Smuzhiyun pwm: pwm@10020000 { 63*4882a593Smuzhiyun compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; 64*4882a593Smuzhiyun reg = <0x10020000 0x1000>; 65*4882a593Smuzhiyun clocks = <&tlclk>; 66*4882a593Smuzhiyun interrupt-parent = <&plic>; 67*4882a593Smuzhiyun interrupts = <42>, <43>, <44>, <45>; 68*4882a593Smuzhiyun #pwm-cells = <3>; 69*4882a593Smuzhiyun }; 70