1*4882a593SmuzhiyunMediaTek display PWM controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: should be "mediatek,<name>-disp-pwm": 5*4882a593Smuzhiyun - "mediatek,mt2701-disp-pwm": found on mt2701 SoC. 6*4882a593Smuzhiyun - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. 7*4882a593Smuzhiyun - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. 8*4882a593Smuzhiyun - reg: physical base address and length of the controller's registers. 9*4882a593Smuzhiyun - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of 10*4882a593Smuzhiyun the cell format. 11*4882a593Smuzhiyun - clocks: phandle and clock specifier of the PWM reference clock. 12*4882a593Smuzhiyun - clock-names: must contain the following: 13*4882a593Smuzhiyun - "main": clock used to generate PWM signals. 14*4882a593Smuzhiyun - "mm": sync signals from the modules of mmsys. 15*4882a593Smuzhiyun - pinctrl-names: Must contain a "default" entry. 16*4882a593Smuzhiyun - pinctrl-0: One property must exist for each entry in pinctrl-names. 17*4882a593Smuzhiyun See pinctrl/pinctrl-bindings.txt for details of the property values. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: 20*4882a593Smuzhiyun pwm0: pwm@1401e000 { 21*4882a593Smuzhiyun compatible = "mediatek,mt8173-disp-pwm", 22*4882a593Smuzhiyun "mediatek,mt6595-disp-pwm"; 23*4882a593Smuzhiyun reg = <0 0x1401e000 0 0x1000>; 24*4882a593Smuzhiyun #pwm-cells = <2>; 25*4882a593Smuzhiyun clocks = <&mmsys CLK_MM_DISP_PWM026M>, 26*4882a593Smuzhiyun <&mmsys CLK_MM_DISP_PWM0MM>; 27*4882a593Smuzhiyun clock-names = "main", "mm"; 28*4882a593Smuzhiyun pinctrl-names = "default"; 29*4882a593Smuzhiyun pinctrl-0 = <&disp_pwm0_pins>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun backlight_lcd: backlight_lcd { 33*4882a593Smuzhiyun compatible = "pwm-backlight"; 34*4882a593Smuzhiyun pwms = <&pwm0 0 1000000>; 35*4882a593Smuzhiyun brightness-levels = < 36*4882a593Smuzhiyun 0 16 32 48 64 80 96 112 37*4882a593Smuzhiyun 128 144 160 176 192 208 224 240 38*4882a593Smuzhiyun 255 39*4882a593Smuzhiyun >; 40*4882a593Smuzhiyun default-brightness-level = <9>; 41*4882a593Smuzhiyun power-supply = <&mt6397_vio18_reg>; 42*4882a593Smuzhiyun enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; 43*4882a593Smuzhiyun }; 44