1*4882a593SmuzhiyunMediaTek PWM controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: should be "mediatek,<name>-pwm": 5*4882a593Smuzhiyun - "mediatek,mt2712-pwm": found on mt2712 SoC. 6*4882a593Smuzhiyun - "mediatek,mt7622-pwm": found on mt7622 SoC. 7*4882a593Smuzhiyun - "mediatek,mt7623-pwm": found on mt7623 SoC. 8*4882a593Smuzhiyun - "mediatek,mt7628-pwm": found on mt7628 SoC. 9*4882a593Smuzhiyun - "mediatek,mt7629-pwm": found on mt7629 SoC. 10*4882a593Smuzhiyun - "mediatek,mt8516-pwm": found on mt8516 SoC. 11*4882a593Smuzhiyun - reg: physical base address and length of the controller's registers. 12*4882a593Smuzhiyun - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of 13*4882a593Smuzhiyun the cell format. 14*4882a593Smuzhiyun - clocks: phandle and clock specifier of the PWM reference clock. 15*4882a593Smuzhiyun - clock-names: must contain the following, except for MT7628 which 16*4882a593Smuzhiyun has no clocks 17*4882a593Smuzhiyun - "top": the top clock generator 18*4882a593Smuzhiyun - "main": clock used by the PWM core 19*4882a593Smuzhiyun - "pwm1-8": the eight per PWM clocks for mt2712 20*4882a593Smuzhiyun - "pwm1-6": the six per PWM clocks for mt7622 21*4882a593Smuzhiyun - "pwm1-5": the five per PWM clocks for mt7623 22*4882a593Smuzhiyun - "pwm1" : the PWM1 clock for mt7629 23*4882a593Smuzhiyun - pinctrl-names: Must contain a "default" entry. 24*4882a593Smuzhiyun - pinctrl-0: One property must exist for each entry in pinctrl-names. 25*4882a593Smuzhiyun See pinctrl/pinctrl-bindings.txt for details of the property values. 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunOptional properties: 28*4882a593Smuzhiyun- assigned-clocks: Reference to the PWM clock entries. 29*4882a593Smuzhiyun- assigned-clock-parents: The phandle of the parent clock of PWM clock. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunExample: 32*4882a593Smuzhiyun pwm0: pwm@11006000 { 33*4882a593Smuzhiyun compatible = "mediatek,mt7623-pwm"; 34*4882a593Smuzhiyun reg = <0 0x11006000 0 0x1000>; 35*4882a593Smuzhiyun #pwm-cells = <2>; 36*4882a593Smuzhiyun clocks = <&topckgen CLK_TOP_PWM_SEL>, 37*4882a593Smuzhiyun <&pericfg CLK_PERI_PWM>, 38*4882a593Smuzhiyun <&pericfg CLK_PERI_PWM1>, 39*4882a593Smuzhiyun <&pericfg CLK_PERI_PWM2>, 40*4882a593Smuzhiyun <&pericfg CLK_PERI_PWM3>, 41*4882a593Smuzhiyun <&pericfg CLK_PERI_PWM4>, 42*4882a593Smuzhiyun <&pericfg CLK_PERI_PWM5>; 43*4882a593Smuzhiyun clock-names = "top", "main", "pwm1", "pwm2", 44*4882a593Smuzhiyun "pwm3", "pwm4", "pwm5"; 45*4882a593Smuzhiyun pinctrl-names = "default"; 46*4882a593Smuzhiyun pinctrl-0 = <&pwm0_pins>; 47*4882a593Smuzhiyun }; 48