1*4882a593SmuzhiyunFreescale FlexTimer Module (FTM) PWM controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe same FTM PWM device can have a different endianness on different SoCs. The 4*4882a593Smuzhiyundevice tree provides a property to describing this so that an operating system 5*4882a593Smuzhiyundevice driver can handle all variants of the device. Refer to the table below 6*4882a593Smuzhiyunfor the endianness of the FTM PWM block as integrated into the existing SoCs: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun SoC | FTM-PWM endianness 9*4882a593Smuzhiyun --------+------------------- 10*4882a593Smuzhiyun Vybrid | LE 11*4882a593Smuzhiyun LS1 | BE 12*4882a593Smuzhiyun LS2 | LE 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunPlease see ../regmap/regmap.txt for more detail about how to specify endian 15*4882a593Smuzhiyunmodes in device tree. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunRequired properties: 19*4882a593Smuzhiyun- compatible : should be "fsl,<soc>-ftm-pwm" and one of the following 20*4882a593Smuzhiyun compatible strings: 21*4882a593Smuzhiyun - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610 22*4882a593Smuzhiyun - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM 23*4882a593Smuzhiyun- reg: Physical base address and length of the controller's registers 24*4882a593Smuzhiyun- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of 25*4882a593Smuzhiyun the cells format. 26*4882a593Smuzhiyun- clock-names: Should include the following module clock source entries: 27*4882a593Smuzhiyun "ftm_sys" (module clock, also can be used as counter clock), 28*4882a593Smuzhiyun "ftm_ext" (external counter clock), 29*4882a593Smuzhiyun "ftm_fix" (fixed counter clock), 30*4882a593Smuzhiyun "ftm_cnt_clk_en" (external and fixed counter clock enable/disable). 31*4882a593Smuzhiyun- clocks: Must contain a phandle and clock specifier for each entry in 32*4882a593Smuzhiyun clock-names, please see clock/clock-bindings.txt for details of the property 33*4882a593Smuzhiyun values. 34*4882a593Smuzhiyun- pinctrl-names: Must contain a "default" entry. 35*4882a593Smuzhiyun- pinctrl-NNN: One property must exist for each entry in pinctrl-names. 36*4882a593Smuzhiyun See pinctrl/pinctrl-bindings.txt for details of the property values. 37*4882a593Smuzhiyun- big-endian: Boolean property, required if the FTM PWM registers use a big- 38*4882a593Smuzhiyun endian rather than little-endian layout. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunpwm0: pwm@40038000 { 43*4882a593Smuzhiyun compatible = "fsl,vf610-ftm-pwm"; 44*4882a593Smuzhiyun reg = <0x40038000 0x1000>; 45*4882a593Smuzhiyun #pwm-cells = <3>; 46*4882a593Smuzhiyun clock-names = "ftm_sys", "ftm_ext", 47*4882a593Smuzhiyun "ftm_fix", "ftm_cnt_clk_en"; 48*4882a593Smuzhiyun clocks = <&clks VF610_CLK_FTM0>, 49*4882a593Smuzhiyun <&clks VF610_CLK_FTM0_EXT_SEL>, 50*4882a593Smuzhiyun <&clks VF610_CLK_FTM0_FIX_SEL>, 51*4882a593Smuzhiyun <&clks VF610_CLK_FTM0_EXT_FIX_EN>; 52*4882a593Smuzhiyun pinctrl-names = "default"; 53*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm0_1>; 54*4882a593Smuzhiyun big-endian; 55*4882a593Smuzhiyun}; 56