1*4882a593SmuzhiyunTegra SoC PWFM controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Must be: 5*4882a593Smuzhiyun - "nvidia,tegra20-pwm": for Tegra20 6*4882a593Smuzhiyun - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30 7*4882a593Smuzhiyun - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114 8*4882a593Smuzhiyun - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124 9*4882a593Smuzhiyun - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132 10*4882a593Smuzhiyun - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210 11*4882a593Smuzhiyun - "nvidia,tegra186-pwm": for Tegra186 12*4882a593Smuzhiyun - "nvidia,tegra194-pwm": for Tegra194 13*4882a593Smuzhiyun- reg: physical base address and length of the controller's registers 14*4882a593Smuzhiyun- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of 15*4882a593Smuzhiyun the cells format. 16*4882a593Smuzhiyun- clocks: Must contain one entry, for the module clock. 17*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 18*4882a593Smuzhiyun- resets: Must contain an entry for each entry in reset-names. 19*4882a593Smuzhiyun See ../reset/reset.txt for details. 20*4882a593Smuzhiyun- reset-names: Must include the following entries: 21*4882a593Smuzhiyun - pwm 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunOptional properties: 24*4882a593Smuzhiyun============================ 25*4882a593SmuzhiyunIn some of the interface like PWM based regulator device, it is required 26*4882a593Smuzhiyunto configure the pins differently in different states, especially in suspend 27*4882a593Smuzhiyunstate of the system. The configuration of pin is provided via the pinctrl 28*4882a593SmuzhiyunDT node as detailed in the pinctrl DT binding document 29*4882a593Smuzhiyun Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunThe PWM node will have following optional properties. 32*4882a593Smuzhiyunpinctrl-names: Pin state names. Must be "default" and "sleep". 33*4882a593Smuzhiyunpinctrl-0: phandle for the default/active state of pin configurations. 34*4882a593Smuzhiyunpinctrl-1: phandle for the sleep state of pin configurations. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunExample: 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun pwm: pwm@7000a000 { 39*4882a593Smuzhiyun compatible = "nvidia,tegra20-pwm"; 40*4882a593Smuzhiyun reg = <0x7000a000 0x100>; 41*4882a593Smuzhiyun #pwm-cells = <2>; 42*4882a593Smuzhiyun clocks = <&tegra_car 17>; 43*4882a593Smuzhiyun resets = <&tegra_car 17>; 44*4882a593Smuzhiyun reset-names = "pwm"; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunExample with the pin configuration for suspend and resume: 49*4882a593Smuzhiyun========================================================= 50*4882a593SmuzhiyunSuppose pin PE7 (On Tegra210) interfaced with the regulator device and 51*4882a593Smuzhiyunit requires PWM output to be tristated when system enters suspend. 52*4882a593SmuzhiyunFollowing will be DT binding to achieve this: 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun#include <dt-bindings/pinctrl/pinctrl-tegra.h> 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun pinmux@700008d4 { 57*4882a593Smuzhiyun pwm_active_state: pwm_active_state { 58*4882a593Smuzhiyun pe7 { 59*4882a593Smuzhiyun nvidia,pins = "pe7"; 60*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun pwm_sleep_state: pwm_sleep_state { 65*4882a593Smuzhiyun pe7 { 66*4882a593Smuzhiyun nvidia,pins = "pe7"; 67*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun pwm@7000a000 { 73*4882a593Smuzhiyun /* Mandatory PWM properties */ 74*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 75*4882a593Smuzhiyun pinctrl-0 = <&pwm_active_state>; 76*4882a593Smuzhiyun pinctrl-1 = <&pwm_sleep_state>; 77*4882a593Smuzhiyun }; 78