1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale i.MX TPM PWM controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Anson Huang <anson.huang@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The TPM counter and period counter are shared between multiple 14*4882a593Smuzhiyun channels, so all channels should use same period setting. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun "#pwm-cells": 18*4882a593Smuzhiyun const: 3 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun enum: 22*4882a593Smuzhiyun - fsl,imx7ulp-pwm 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun reg: 25*4882a593Smuzhiyun maxItems: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun assigned-clocks: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun assigned-clock-parents: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunrequired: 37*4882a593Smuzhiyun - "#pwm-cells" 38*4882a593Smuzhiyun - compatible 39*4882a593Smuzhiyun - reg 40*4882a593Smuzhiyun - clocks 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunadditionalProperties: false 43*4882a593Smuzhiyun 44*4882a593Smuzhiyunexamples: 45*4882a593Smuzhiyun - | 46*4882a593Smuzhiyun #include <dt-bindings/clock/imx7ulp-clock.h> 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun pwm@40250000 { 49*4882a593Smuzhiyun compatible = "fsl,imx7ulp-pwm"; 50*4882a593Smuzhiyun reg = <0x40250000 0x1000>; 51*4882a593Smuzhiyun assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; 52*4882a593Smuzhiyun assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; 53*4882a593Smuzhiyun clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; 54*4882a593Smuzhiyun #pwm-cells = <3>; 55*4882a593Smuzhiyun }; 56