1*4882a593Smuzhiyun* Freescale Serial RapidIO (SRIO) Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRapidIO port node: 4*4882a593SmuzhiyunProperties: 5*4882a593Smuzhiyun - compatible 6*4882a593Smuzhiyun Usage: required 7*4882a593Smuzhiyun Value type: <string> 8*4882a593Smuzhiyun Definition: Must include "fsl,srio" for IP blocks with IP Block 9*4882a593Smuzhiyun Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun Optionally, a compatible string of "fsl,srio-vX.Y" where X is Major 12*4882a593Smuzhiyun version in IP Block Revision Register and Y is Minor version. If this 13*4882a593Smuzhiyun compatible is provided it should be ordered before "fsl,srio". 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun - reg 16*4882a593Smuzhiyun Usage: required 17*4882a593Smuzhiyun Value type: <prop-encoded-array> 18*4882a593Smuzhiyun Definition: A standard property. Specifies the physical address and 19*4882a593Smuzhiyun length of the SRIO configuration registers. The size should 20*4882a593Smuzhiyun be set to 0x11000. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun - interrupts 23*4882a593Smuzhiyun Usage: required 24*4882a593Smuzhiyun Value type: <prop_encoded-array> 25*4882a593Smuzhiyun Definition: Specifies the interrupts generated by this device. The 26*4882a593Smuzhiyun value of the interrupts property consists of one interrupt 27*4882a593Smuzhiyun specifier. The format of the specifier is defined by the 28*4882a593Smuzhiyun binding document describing the node's interrupt parent. 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun A single IRQ that handles error conditions is specified by this 31*4882a593Smuzhiyun property. (Typically shared with port-write). 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun - fsl,srio-rmu-handle: 34*4882a593Smuzhiyun Usage: required if rmu node is defined 35*4882a593Smuzhiyun Value type: <phandle> 36*4882a593Smuzhiyun Definition: A single <phandle> value that points to the RMU. 37*4882a593Smuzhiyun (See srio-rmu.txt for more details on RMU node binding) 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunPort Child Nodes: There should a port child node for each port that exists in 40*4882a593Smuzhiyunthe controller. The ports are numbered starting at one (1) and should have 41*4882a593Smuzhiyunthe following properties: 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun - cell-index 44*4882a593Smuzhiyun Usage: required 45*4882a593Smuzhiyun Value type: <u32> 46*4882a593Smuzhiyun Definition: A standard property. Matches the port id. 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun - ranges 49*4882a593Smuzhiyun Usage: required if local access windows preset 50*4882a593Smuzhiyun Value type: <prop-encoded-array> 51*4882a593Smuzhiyun Definition: A standard property. Utilized to describe the memory mapped 52*4882a593Smuzhiyun IO space utilized by the controller. This corresponds to the 53*4882a593Smuzhiyun setting of the local access windows that are targeted to this 54*4882a593Smuzhiyun SRIO port. 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun - fsl,liodn 57*4882a593Smuzhiyun Usage: optional-but-recommended (for devices with PAMU) 58*4882a593Smuzhiyun Value type: <prop-encoded-array> 59*4882a593Smuzhiyun Definition: The logical I/O device number for the PAMU (IOMMU) to be 60*4882a593Smuzhiyun correctly configured for SRIO accesses. The property should 61*4882a593Smuzhiyun not exist on devices that do not support PAMU. 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun For HW (ie, the P4080) that only supports a LIODN for both 64*4882a593Smuzhiyun memory and maintenance transactions then a single LIODN is 65*4882a593Smuzhiyun represented in the property for both transactions. 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun For HW (ie, the P304x/P5020, etc) that supports an LIODN for 68*4882a593Smuzhiyun memory transactions and a unique LIODN for maintenance 69*4882a593Smuzhiyun transactions then a pair of LIODNs are represented in the 70*4882a593Smuzhiyun property. Within the pair, the first element represents the 71*4882a593Smuzhiyun LIODN associated with memory transactions and the second element 72*4882a593Smuzhiyun represents the LIODN associated with maintenance transactions 73*4882a593Smuzhiyun for the port. 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunNote: All other standard properties (see the Devicetree Specification) 76*4882a593Smuzhiyunare allowed but are optional. 77*4882a593Smuzhiyun 78*4882a593SmuzhiyunExample: 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun rapidio: rapidio@ffe0c0000 { 81*4882a593Smuzhiyun #address-cells = <2>; 82*4882a593Smuzhiyun #size-cells = <2>; 83*4882a593Smuzhiyun reg = <0xf 0xfe0c0000 0 0x11000>; 84*4882a593Smuzhiyun compatible = "fsl,srio"; 85*4882a593Smuzhiyun interrupts = <16 2 1 11>; /* err_irq */ 86*4882a593Smuzhiyun fsl,srio-rmu-handle = <&rmu>; 87*4882a593Smuzhiyun ranges; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun port1 { 90*4882a593Smuzhiyun cell-index = <1>; 91*4882a593Smuzhiyun #address-cells = <2>; 92*4882a593Smuzhiyun #size-cells = <2>; 93*4882a593Smuzhiyun fsl,liodn = <34>; 94*4882a593Smuzhiyun ranges = <0 0 0xc 0x20000000 0 0x10000000>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun port2 { 98*4882a593Smuzhiyun cell-index = <2>; 99*4882a593Smuzhiyun #address-cells = <2>; 100*4882a593Smuzhiyun #size-cells = <2>; 101*4882a593Smuzhiyun fsl,liodn = <48>; 102*4882a593Smuzhiyun ranges = <0 0 0xc 0x30000000 0 0x10000000>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun }; 105