1*4882a593Smuzhiyun* Power Management Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunProperties: 4*4882a593Smuzhiyun- compatible: "fsl,<chip>-pmc". 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun "fsl,mpc8349-pmc" should be listed for any chip whose PMC is 7*4882a593Smuzhiyun compatible. "fsl,mpc8313-pmc" should also be listed for any chip 8*4882a593Smuzhiyun whose PMC is compatible, and implies deep-sleep capability. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun "fsl,mpc8548-pmc" should be listed for any chip whose PMC is 11*4882a593Smuzhiyun compatible. "fsl,mpc8536-pmc" should also be listed for any chip 12*4882a593Smuzhiyun whose PMC is compatible, and implies deep-sleep capability. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is 15*4882a593Smuzhiyun compatible; all statements below that apply to "fsl,mpc8548-pmc" also 16*4882a593Smuzhiyun apply to "fsl,mpc8641d-pmc". 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these 19*4882a593Smuzhiyun bit assignments are indicated via the sleep specifier in each device's 20*4882a593Smuzhiyun sleep property. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource 23*4882a593Smuzhiyun is the PMC block, and the second resource is the Clock Configuration 24*4882a593Smuzhiyun block. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun For devices compatible with "fsl,mpc8548-pmc", the first resource 27*4882a593Smuzhiyun is a 32-byte block beginning with DEVDISR. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first 30*4882a593Smuzhiyun resource is the PMC block interrupt. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices, 33*4882a593Smuzhiyun this is a phandle to an "fsl,gtm" node on which timer 4 can be used as 34*4882a593Smuzhiyun a wakeup source from deep sleep. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunSleep specifiers: 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit 39*4882a593Smuzhiyun that is set in the cell, the corresponding bit in SCCR will be saved 40*4882a593Smuzhiyun and cleared on suspend, and restored on resume. This sleep controller 41*4882a593Smuzhiyun supports disabling and resuming devices at any time. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of 44*4882a593Smuzhiyun which will be ORed into PMCDR upon suspend, and cleared from PMCDR 45*4882a593Smuzhiyun upon resume. The first two cells are as described for fsl,mpc8578-pmc. 46*4882a593Smuzhiyun This sleep controller only supports disabling devices during system 47*4882a593Smuzhiyun sleep, or permanently. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the 50*4882a593Smuzhiyun first of which will be ORed into DEVDISR (and the second into 51*4882a593Smuzhiyun DEVDISR2, if present -- this cell should be zero or absent if the 52*4882a593Smuzhiyun hardware does not have DEVDISR2) upon a request for permanent device 53*4882a593Smuzhiyun disabling. This sleep controller does not support configuring devices 54*4882a593Smuzhiyun to disable during system sleep (unless supported by another compatible 55*4882a593Smuzhiyun match), or dynamically. 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunExample: 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun power@b00 { 60*4882a593Smuzhiyun compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; 61*4882a593Smuzhiyun reg = <0xb00 0x100 0xa00 0x100>; 62*4882a593Smuzhiyun interrupts = <80 8>; 63*4882a593Smuzhiyun }; 64