1*4882a593Smuzhiyun* Freescale MPIC timers 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "fsl,mpic-global-timer" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun- reg : Contains two regions. The first is the main timer register bank 7*4882a593Smuzhiyun (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control 8*4882a593Smuzhiyun register (TCRx) for the group. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- fsl,available-ranges: use <start count> style section to define which 11*4882a593Smuzhiyun timer interrupts can be used. This property is optional; without this, 12*4882a593Smuzhiyun all timers within the group can be used. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- interrupts: one interrupt per timer in the group, in order, starting 15*4882a593Smuzhiyun with timer zero. If timer-available-ranges is present, only the 16*4882a593Smuzhiyun interrupts that correspond to available timers shall be present. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun /* Note that this requires #interrupt-cells to be 4 */ 20*4882a593Smuzhiyun timer0: timer@41100 { 21*4882a593Smuzhiyun compatible = "fsl,mpic-global-timer"; 22*4882a593Smuzhiyun reg = <0x41100 0x100 0x41300 4>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Another AMP partition is using timers 0 and 1 */ 25*4882a593Smuzhiyun fsl,available-ranges = <2 2>; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun interrupts = <2 0 3 0 28*4882a593Smuzhiyun 3 0 3 0>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun timer1: timer@42100 { 32*4882a593Smuzhiyun compatible = "fsl,mpic-global-timer"; 33*4882a593Smuzhiyun reg = <0x42100 0x100 0x42300 4>; 34*4882a593Smuzhiyun interrupts = <4 0 3 0 35*4882a593Smuzhiyun 5 0 3 0 36*4882a593Smuzhiyun 6 0 3 0 37*4882a593Smuzhiyun 7 0 3 0>; 38*4882a593Smuzhiyun }; 39