1*4882a593Smuzhiyun* FSL MPIC Message Registers 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding specifies what properties must be available in the device tree 4*4882a593Smuzhiyunrepresentation of the message register blocks found in some FSL MPIC 5*4882a593Smuzhiyunimplementations. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun - compatible: Specifies the compatibility list for the message register 10*4882a593Smuzhiyun block. The type shall be <string-list> and the value shall be of the form 11*4882a593Smuzhiyun "fsl,mpic-v<version>-msgr", where <version> is the version number of 12*4882a593Smuzhiyun the MPIC containing the message registers. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun - reg: Specifies the base physical address(s) and size(s) of the 15*4882a593Smuzhiyun message register block's addressable register space. The type shall be 16*4882a593Smuzhiyun <prop-encoded-array>. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun - interrupts: Specifies a list of interrupt-specifiers which are available 19*4882a593Smuzhiyun for receiving interrupts. Interrupt-specifier consists of two cells: first 20*4882a593Smuzhiyun cell is interrupt-number and second cell is level-sense. The type shall be 21*4882a593Smuzhiyun <prop-encoded-array>. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunOptional properties: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun - mpic-msgr-receive-mask: Specifies what registers in the containing block 26*4882a593Smuzhiyun are allowed to receive interrupts. The value is a bit mask where a set 27*4882a593Smuzhiyun bit at bit 'n' indicates that message register 'n' can receive interrupts. 28*4882a593Smuzhiyun Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall 29*4882a593Smuzhiyun be <u32>. If not present, then all of the message registers in the block 30*4882a593Smuzhiyun are available. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunAliases: 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun An alias should be created for every message register block. They are not 35*4882a593Smuzhiyun required, though. However, a particular implementation of this binding 36*4882a593Smuzhiyun may require aliases to be present. Aliases are of the form 37*4882a593Smuzhiyun 'mpic-msgr-block<n>', where <n> is an integer specifying the block's number. 38*4882a593Smuzhiyun Numbers shall start at 0. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun aliases { 43*4882a593Smuzhiyun mpic-msgr-block0 = &mpic_msgr_block0; 44*4882a593Smuzhiyun mpic-msgr-block1 = &mpic_msgr_block1; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun mpic_msgr_block0: mpic-msgr-block@41400 { 48*4882a593Smuzhiyun compatible = "fsl,mpic-v3.1-msgr"; 49*4882a593Smuzhiyun reg = <0x41400 0x200>; 50*4882a593Smuzhiyun // Message registers 0 and 2 in this block can receive interrupts on 51*4882a593Smuzhiyun // sources 0xb0 and 0xb2, respectively. 52*4882a593Smuzhiyun interrupts = <0xb0 2 0xb2 2>; 53*4882a593Smuzhiyun mpic-msgr-receive-mask = <0x5>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun mpic_msgr_block1: mpic-msgr-block@42400 { 57*4882a593Smuzhiyun compatible = "fsl,mpic-v3.1-msgr"; 58*4882a593Smuzhiyun reg = <0x42400 0x200>; 59*4882a593Smuzhiyun // Message registers 0 and 2 in this block can receive interrupts on 60*4882a593Smuzhiyun // sources 0xb4 and 0xb6, respectively. 61*4882a593Smuzhiyun interrupts = <0xb4 2 0xb6 2>; 62*4882a593Smuzhiyun mpic-msgr-receive-mask = <0x5>; 63*4882a593Smuzhiyun }; 64