1*4882a593SmuzhiyunMPC5121 PSC Device Tree Bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunPSC in UART mode 4*4882a593Smuzhiyun---------------- 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunFor PSC in UART mode the needed PSC serial devices 7*4882a593Smuzhiyunare specified by fsl,mpc5121-psc-uart nodes in the 8*4882a593Smuzhiyunfsl,mpc5121-immr SoC node. Additionally the PSC FIFO 9*4882a593SmuzhiyunController node fsl,mpc5121-psc-fifo is required there: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyunfsl,mpc512x-psc-uart nodes 12*4882a593Smuzhiyun-------------------------- 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired properties : 15*4882a593Smuzhiyun - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc" 16*4882a593Smuzhiyun Supported <soc>s: mpc5121, mpc5125 17*4882a593Smuzhiyun - reg : Offset and length of the register set for the PSC device 18*4882a593Smuzhiyun - interrupts : <a b> where a is the interrupt number of the 19*4882a593Smuzhiyun PSC FIFO Controller and b is a field that represents an 20*4882a593Smuzhiyun encoding of the sense and level information for the interrupt. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunRecommended properties : 23*4882a593Smuzhiyun - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4) 24*4882a593Smuzhiyun - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4) 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunPSC in SPI mode 27*4882a593Smuzhiyun--------------- 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunSimilar to the UART mode a PSC can be operated in SPI mode. The compatible used 30*4882a593Smuzhiyunfor that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well. 31*4882a593SmuzhiyunThe required and recommended properties are identical to the 32*4882a593Smuzhiyunfsl,mpc5121-psc-uart nodes, just use spi instead of uart in the compatible 33*4882a593Smuzhiyunstring. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunfsl,mpc512x-psc-fifo node 36*4882a593Smuzhiyun------------------------- 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunRequired properties : 39*4882a593Smuzhiyun - compatible : Should be "fsl,<soc>-psc-fifo" 40*4882a593Smuzhiyun Supported <soc>s: mpc5121, mpc5125 41*4882a593Smuzhiyun - reg : Offset and length of the register set for the PSC 42*4882a593Smuzhiyun FIFO Controller 43*4882a593Smuzhiyun - interrupts : <a b> where a is the interrupt number of the 44*4882a593Smuzhiyun PSC FIFO Controller and b is a field that represents an 45*4882a593Smuzhiyun encoding of the sense and level information for the interrupt. 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunRecommended properties : 48*4882a593Smuzhiyun - clocks : specifies the clock needed to operate the fifo controller 49*4882a593Smuzhiyun - clock-names : name(s) for the clock(s) listed in clocks 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunExample for a board using PSC0 and PSC1 devices in serial mode: 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunserial@11000 { 54*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 55*4882a593Smuzhiyun cell-index = <0>; 56*4882a593Smuzhiyun reg = <0x11000 0x100>; 57*4882a593Smuzhiyun interrupts = <40 0x8>; 58*4882a593Smuzhiyun interrupt-parent = < &ipic >; 59*4882a593Smuzhiyun fsl,rx-fifo-size = <16>; 60*4882a593Smuzhiyun fsl,tx-fifo-size = <16>; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunserial@11100 { 64*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 65*4882a593Smuzhiyun cell-index = <1>; 66*4882a593Smuzhiyun reg = <0x11100 0x100>; 67*4882a593Smuzhiyun interrupts = <40 0x8>; 68*4882a593Smuzhiyun interrupt-parent = < &ipic >; 69*4882a593Smuzhiyun fsl,rx-fifo-size = <16>; 70*4882a593Smuzhiyun fsl,tx-fifo-size = <16>; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyunpscfifo@11f00 { 74*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-fifo"; 75*4882a593Smuzhiyun reg = <0x11f00 0x100>; 76*4882a593Smuzhiyun interrupts = <40 0x8>; 77*4882a593Smuzhiyun interrupt-parent = < &ipic >; 78*4882a593Smuzhiyun}; 79