1*4882a593SmuzhiyunFreescale L2 Cache Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunL2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. 4*4882a593SmuzhiyunThe cache bindings explained below are Devicetree Specification compliant 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired Properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible : Should include one of the following: 9*4882a593Smuzhiyun "fsl,8540-l2-cache-controller" 10*4882a593Smuzhiyun "fsl,8541-l2-cache-controller" 11*4882a593Smuzhiyun "fsl,8544-l2-cache-controller" 12*4882a593Smuzhiyun "fsl,8548-l2-cache-controller" 13*4882a593Smuzhiyun "fsl,8555-l2-cache-controller" 14*4882a593Smuzhiyun "fsl,8568-l2-cache-controller" 15*4882a593Smuzhiyun "fsl,b4420-l2-cache-controller" 16*4882a593Smuzhiyun "fsl,b4860-l2-cache-controller" 17*4882a593Smuzhiyun "fsl,bsc9131-l2-cache-controller" 18*4882a593Smuzhiyun "fsl,bsc9132-l2-cache-controller" 19*4882a593Smuzhiyun "fsl,c293-l2-cache-controller" 20*4882a593Smuzhiyun "fsl,mpc8536-l2-cache-controller" 21*4882a593Smuzhiyun "fsl,mpc8540-l2-cache-controller" 22*4882a593Smuzhiyun "fsl,mpc8541-l2-cache-controller" 23*4882a593Smuzhiyun "fsl,mpc8544-l2-cache-controller" 24*4882a593Smuzhiyun "fsl,mpc8548-l2-cache-controller" 25*4882a593Smuzhiyun "fsl,mpc8555-l2-cache-controller" 26*4882a593Smuzhiyun "fsl,mpc8560-l2-cache-controller" 27*4882a593Smuzhiyun "fsl,mpc8568-l2-cache-controller" 28*4882a593Smuzhiyun "fsl,mpc8569-l2-cache-controller" 29*4882a593Smuzhiyun "fsl,mpc8572-l2-cache-controller" 30*4882a593Smuzhiyun "fsl,p1010-l2-cache-controller" 31*4882a593Smuzhiyun "fsl,p1011-l2-cache-controller" 32*4882a593Smuzhiyun "fsl,p1012-l2-cache-controller" 33*4882a593Smuzhiyun "fsl,p1013-l2-cache-controller" 34*4882a593Smuzhiyun "fsl,p1014-l2-cache-controller" 35*4882a593Smuzhiyun "fsl,p1015-l2-cache-controller" 36*4882a593Smuzhiyun "fsl,p1016-l2-cache-controller" 37*4882a593Smuzhiyun "fsl,p1020-l2-cache-controller" 38*4882a593Smuzhiyun "fsl,p1021-l2-cache-controller" 39*4882a593Smuzhiyun "fsl,p1022-l2-cache-controller" 40*4882a593Smuzhiyun "fsl,p1023-l2-cache-controller" 41*4882a593Smuzhiyun "fsl,p1024-l2-cache-controller" 42*4882a593Smuzhiyun "fsl,p1025-l2-cache-controller" 43*4882a593Smuzhiyun "fsl,p2010-l2-cache-controller" 44*4882a593Smuzhiyun "fsl,p2020-l2-cache-controller" 45*4882a593Smuzhiyun "fsl,t2080-l2-cache-controller" 46*4882a593Smuzhiyun "fsl,t4240-l2-cache-controller" 47*4882a593Smuzhiyun and "cache". 48*4882a593Smuzhiyun- reg : Address and size of L2 cache controller registers 49*4882a593Smuzhiyun- cache-size : Size of the entire L2 cache 50*4882a593Smuzhiyun- interrupts : Error interrupt of L2 controller 51*4882a593Smuzhiyun- cache-line-size : Size of L2 cache lines 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunExample: 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun L2: l2-cache-controller@20000 { 56*4882a593Smuzhiyun compatible = "fsl,bsc9132-l2-cache-controller", "cache"; 57*4882a593Smuzhiyun reg = <0x20000 0x1000>; 58*4882a593Smuzhiyun cache-line-size = <32>; // 32 bytes 59*4882a593Smuzhiyun cache-size = <0x40000>; // L2,256K 60*4882a593Smuzhiyun interrupts = <16 2 1 0>; 61*4882a593Smuzhiyun }; 62