1*4882a593Smuzhiyun* Freescale PQ3 and QorIQ based Cache SRAM 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunFreescale's mpc85xx and some QorIQ platforms provide an 4*4882a593Smuzhiyunoption of configuring a part of (or full) cache memory 5*4882a593Smuzhiyunas SRAM. This cache SRAM representation in the device 6*4882a593Smuzhiyuntree should be done as under:- 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- compatible : should be "fsl,p2020-cache-sram" 11*4882a593Smuzhiyun- fsl,cache-sram-ctlr-handle : points to the L2 controller 12*4882a593Smuzhiyun- reg : offset and length of the cache-sram. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunExample: 15*4882a593Smuzhiyun 16*4882a593Smuzhiyuncache-sram@fff00000 { 17*4882a593Smuzhiyun fsl,cache-sram-ctlr-handle = <&L2>; 18*4882a593Smuzhiyun reg = <0 0xfff00000 0 0x10000>; 19*4882a593Smuzhiyun compatible = "fsl,p2020-cache-sram"; 20*4882a593Smuzhiyun}; 21