1*4882a593SmuzhiyunPPC440SPe DMA/XOR (DMA Controller and XOR Accelerator) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunDevice nodes needed for operation of the ppc440spe-adma driver 4*4882a593Smuzhiyunare specified hereby. These are I2O/DMA, DMA and XOR nodes 5*4882a593Smuzhiyunfor DMA engines and Memory Queue Module node. The latter is used 6*4882a593Smuzhiyunby ADMA driver for configuration of RAID-6 H/W capabilities of 7*4882a593Smuzhiyunthe PPC440SPe. In addition to the nodes and properties described 8*4882a593Smuzhiyunbelow, the ranges property of PLB node must specify ranges for 9*4882a593SmuzhiyunDMA devices. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun i) The I2O node 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun Required properties: 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun - compatible : "ibm,i2o-440spe"; 16*4882a593Smuzhiyun - reg : <registers mapping> 17*4882a593Smuzhiyun - dcr-reg : <DCR registers range> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun Example: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun I2O: i2o@400100000 { 22*4882a593Smuzhiyun compatible = "ibm,i2o-440spe"; 23*4882a593Smuzhiyun reg = <0x00000004 0x00100000 0x100>; 24*4882a593Smuzhiyun dcr-reg = <0x060 0x020>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun ii) The DMA node 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun Required properties: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun - compatible : "ibm,dma-440spe"; 33*4882a593Smuzhiyun - cell-index : 1 cell, hardware index of the DMA engine 34*4882a593Smuzhiyun (typically 0x0 and 0x1 for DMA0 and DMA1) 35*4882a593Smuzhiyun - reg : <registers mapping> 36*4882a593Smuzhiyun - dcr-reg : <DCR registers range> 37*4882a593Smuzhiyun - interrupts : <interrupt mapping for DMA0/1 interrupts sources: 38*4882a593Smuzhiyun 2 sources: DMAx CS FIFO Needs Service IRQ (on UIC0) 39*4882a593Smuzhiyun and DMA Error IRQ (on UIC1). The latter is common 40*4882a593Smuzhiyun for both DMA engines>. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun Example: 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun DMA0: dma0@400100100 { 45*4882a593Smuzhiyun compatible = "ibm,dma-440spe"; 46*4882a593Smuzhiyun cell-index = <0>; 47*4882a593Smuzhiyun reg = <0x00000004 0x00100100 0x100>; 48*4882a593Smuzhiyun dcr-reg = <0x060 0x020>; 49*4882a593Smuzhiyun interrupt-parent = <&DMA0>; 50*4882a593Smuzhiyun interrupts = <0 1>; 51*4882a593Smuzhiyun #interrupt-cells = <1>; 52*4882a593Smuzhiyun #address-cells = <0>; 53*4882a593Smuzhiyun #size-cells = <0>; 54*4882a593Smuzhiyun interrupt-map = < 55*4882a593Smuzhiyun 0 &UIC0 0x14 4 56*4882a593Smuzhiyun 1 &UIC1 0x16 4>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun iii) XOR Accelerator node 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun Required properties: 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun - compatible : "amcc,xor-accelerator"; 65*4882a593Smuzhiyun - reg : <registers mapping> 66*4882a593Smuzhiyun - interrupts : <interrupt mapping for XOR interrupt source> 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun Example: 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun xor-accel@400200000 { 71*4882a593Smuzhiyun compatible = "amcc,xor-accelerator"; 72*4882a593Smuzhiyun reg = <0x00000004 0x00200000 0x400>; 73*4882a593Smuzhiyun interrupt-parent = <&UIC1>; 74*4882a593Smuzhiyun interrupts = <0x1f 4>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun iv) Memory Queue Module node 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun Required properties: 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun - compatible : "ibm,mq-440spe"; 83*4882a593Smuzhiyun - dcr-reg : <DCR registers range> 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun Example: 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun MQ0: mq { 88*4882a593Smuzhiyun compatible = "ibm,mq-440spe"; 89*4882a593Smuzhiyun dcr-reg = <0x040 0x020>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92