xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593SmuzhiyunMicrosemi Ocelot reset controller
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3*4882a593SmuzhiyunThe DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
4*4882a593SmuzhiyunSoC core.
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6*4882a593SmuzhiyunThe reset registers are both present in the MSCC vcoreiii MIPS and
7*4882a593Smuzhiyunmicrochip Sparx5 armv8 SoC's.
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9*4882a593SmuzhiyunRequired Properties:
10*4882a593Smuzhiyun - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"
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12*4882a593SmuzhiyunExample:
13*4882a593Smuzhiyun	reset@1070008 {
14*4882a593Smuzhiyun		compatible = "mscc,ocelot-chip-reset";
15*4882a593Smuzhiyun		reg = <0x1070008 0x4>;
16*4882a593Smuzhiyun	};
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