xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/mali-opp.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
2*4882a593Smuzhiyun#
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4*4882a593Smuzhiyun#
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13*4882a593Smuzhiyun# GNU General Public License for more details.
14*4882a593Smuzhiyun#
15*4882a593Smuzhiyun# You should have received a copy of the GNU General Public License
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17*4882a593Smuzhiyun# http://www.gnu.org/licenses/gpl-2.0.html.
18*4882a593Smuzhiyun#
19*4882a593Smuzhiyun#
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun* ARM Mali Midgard OPP
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun* OPP Table Node
25*4882a593Smuzhiyun
26*4882a593SmuzhiyunThis describes the OPPs belonging to a device. This node can have following
27*4882a593Smuzhiyunproperties:
28*4882a593Smuzhiyun
29*4882a593SmuzhiyunRequired properties:
30*4882a593Smuzhiyun- compatible: Allow OPPs to express their compatibility. It should be:
31*4882a593Smuzhiyun  "operating-points-v2", "operating-points-v2-mali".
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun- OPP nodes: One or more OPP nodes describing voltage-current-frequency
34*4882a593Smuzhiyun  combinations. Their name isn't significant but their phandle can be used to
35*4882a593Smuzhiyun  reference an OPP.
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun* OPP Node
38*4882a593Smuzhiyun
39*4882a593SmuzhiyunThis defines voltage-current-frequency combinations along with other related
40*4882a593Smuzhiyunproperties.
41*4882a593Smuzhiyun
42*4882a593SmuzhiyunRequired properties:
43*4882a593Smuzhiyun- opp-hz: Nominal frequency in Hz, expressed as a 64-bit big-endian integer.
44*4882a593Smuzhiyun  This should be treated as a relative performance measurement, taking both GPU
45*4882a593Smuzhiyun  frequency and core mask into account.
46*4882a593Smuzhiyun
47*4882a593SmuzhiyunOptional properties:
48*4882a593Smuzhiyun- opp-hz-real: List of one or two real frequencies in Hz, expressed as 64-bit
49*4882a593Smuzhiyun  big-endian integers. They shall correspond to the clocks declared under
50*4882a593Smuzhiyun  the Mali device node, and follow the same order.
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun- opp-core-mask: Shader core mask. If neither this or opp-core-count are present
53*4882a593Smuzhiyun  then all shader cores will be used for this OPP.
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun- opp-core-count: Number of cores to use for this OPP. If this is present then
56*4882a593Smuzhiyun  the driver will build a core mask using the available core mask provided by
57*4882a593Smuzhiyun  the GPU hardware. An opp-core-count value of 0 is not permitted.
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun  If neither this nor opp-core-mask are present then all shader cores will be
60*4882a593Smuzhiyun  used for this OPP.
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun  If both this and opp-core-mask are present then opp-core-mask is ignored.
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun- opp-microvolt: List of one or two voltages in micro Volts. They shall correspond
65*4882a593Smuzhiyun  to the regulators declared under the Mali device node, and follow the order:
66*4882a593Smuzhiyun  "logic", "memory".
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun  A single regulator's voltage is specified with an array of size one or three.
69*4882a593Smuzhiyun  Single entry is for target voltage and three entries are for <target min max>
70*4882a593Smuzhiyun  voltages.
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun  Entries for multiple regulators must be present in the same order as
73*4882a593Smuzhiyun  regulators are specified in device's DT node.
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun- opp-microvolt-<name>: Named opp-microvolt property. This is exactly similar to
76*4882a593Smuzhiyun  the above opp-microvolt property, but allows multiple voltage ranges to be
77*4882a593Smuzhiyun  provided for the same OPP. At runtime, the platform can pick a <name> and
78*4882a593Smuzhiyun  matching opp-microvolt-<name> property will be enabled for all OPPs. If the
79*4882a593Smuzhiyun  platform doesn't pick a specific <name> or the <name> doesn't match with any
80*4882a593Smuzhiyun  opp-microvolt-<name> properties, then opp-microvolt property shall be used, if
81*4882a593Smuzhiyun  present.
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun- opp-microamp: The maximum current drawn by the device in microamperes
84*4882a593Smuzhiyun  considering system specific parameters (such as transients, process, aging,
85*4882a593Smuzhiyun  maximum operating temperature range etc.) as necessary. This may be used to
86*4882a593Smuzhiyun  set the most efficient regulator operating mode.
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun  Should only be set if opp-microvolt is set for the OPP.
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun  Entries for multiple regulators must be present in the same order as
91*4882a593Smuzhiyun  regulators are specified in device's DT node. If this property isn't required
92*4882a593Smuzhiyun  for few regulators, then this should be marked as zero for them. If it isn't
93*4882a593Smuzhiyun  required for any regulator, then this property need not be present.
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun- opp-microamp-<name>: Named opp-microamp property. Similar to
96*4882a593Smuzhiyun  opp-microvolt-<name> property, but for microamp instead.
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun- clock-latency-ns: Specifies the maximum possible transition latency (in
99*4882a593Smuzhiyun  nanoseconds) for switching to this OPP from any other OPP.
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun- turbo-mode: Marks the OPP to be used only for turbo modes. Turbo mode is
102*4882a593Smuzhiyun  available on some platforms, where the device can run over its operating
103*4882a593Smuzhiyun  frequency for a short duration of time limited by the device's power, current
104*4882a593Smuzhiyun  and thermal limits.
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun- opp-suspend: Marks the OPP to be used during device suspend. Only one OPP in
107*4882a593Smuzhiyun  the table should have this.
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun- opp-mali-errata-1485982: Marks the OPP to be selected for suspend clock.
110*4882a593Smuzhiyun  This will be effective only if MALI_HW_ERRATA_1485982_USE_CLOCK_ALTERNATIVE is
111*4882a593Smuzhiyun  enabled. It needs to be placed in any OPP that has proper suspend clock for
112*4882a593Smuzhiyun  the HW workaround.
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun- opp-supported-hw: This enables us to select only a subset of OPPs from the
115*4882a593Smuzhiyun  larger OPP table, based on what version of the hardware we are running on. We
116*4882a593Smuzhiyun  still can't have multiple nodes with the same opp-hz value in OPP table.
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun  It's an user defined array containing a hierarchy of hardware version numbers,
119*4882a593Smuzhiyun  supported by the OPP. For example: a platform with hierarchy of three levels
120*4882a593Smuzhiyun  of versions (A, B and C), this field should be like <X Y Z>, where X
121*4882a593Smuzhiyun  corresponds to Version hierarchy A, Y corresponds to version hierarchy B and Z
122*4882a593Smuzhiyun  corresponds to version hierarchy C.
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun  Each level of hierarchy is represented by a 32 bit value, and so there can be
125*4882a593Smuzhiyun  only 32 different supported version per hierarchy. i.e. 1 bit per version. A
126*4882a593Smuzhiyun  value of 0xFFFFFFFF will enable the OPP for all versions for that hierarchy
127*4882a593Smuzhiyun  level. And a value of 0x00000000 will disable the OPP completely, and so we
128*4882a593Smuzhiyun  never want that to happen.
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun  If 32 values aren't sufficient for a version hierarchy, than that version
131*4882a593Smuzhiyun  hierarchy can be contained in multiple 32 bit values. i.e. <X Y Z1 Z2> in the
132*4882a593Smuzhiyun  above example, Z1 & Z2 refer to the version hierarchy Z.
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun- status: Marks the node enabled/disabled.
135*4882a593Smuzhiyun
136*4882a593SmuzhiyunExample for a Juno with 1 clock and 1 regulator:
137*4882a593Smuzhiyun
138*4882a593Smuzhiyungpu_opp_table: opp_table0 {
139*4882a593Smuzhiyun	compatible = "operating-points-v2", "operating-points-v2-mali";
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun	opp@112500000 {
142*4882a593Smuzhiyun		opp-hz = /bits/ 64 <112500000>;
143*4882a593Smuzhiyun		opp-hz-real = /bits/ 64 <450000000>;
144*4882a593Smuzhiyun		opp-microvolt = <820000>;
145*4882a593Smuzhiyun		opp-core-mask = /bits/ 64 <0x1>;
146*4882a593Smuzhiyun		opp-suspend;
147*4882a593Smuzhiyun		opp-mali-errata-1485982;
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun	opp@225000000 {
150*4882a593Smuzhiyun		opp-hz = /bits/ 64 <225000000>;
151*4882a593Smuzhiyun		opp-hz-real = /bits/ 64 <450000000>;
152*4882a593Smuzhiyun		opp-microvolt = <820000>;
153*4882a593Smuzhiyun		opp-core-count = <2>;
154*4882a593Smuzhiyun	};
155*4882a593Smuzhiyun	opp@450000000 {
156*4882a593Smuzhiyun		opp-hz = /bits/ 64 <450000000>;
157*4882a593Smuzhiyun		opp-hz-real = /bits/ 64 <450000000>;
158*4882a593Smuzhiyun		opp-microvolt = <820000>;
159*4882a593Smuzhiyun		opp-core-mask = /bits/ 64 <0xf>;
160*4882a593Smuzhiyun	};
161*4882a593Smuzhiyun	opp@487500000 {
162*4882a593Smuzhiyun		opp-hz = /bits/ 64 <487500000>;
163*4882a593Smuzhiyun		opp-microvolt = <825000>;
164*4882a593Smuzhiyun	};
165*4882a593Smuzhiyun	opp@525000000 {
166*4882a593Smuzhiyun		opp-hz = /bits/ 64 <525000000>;
167*4882a593Smuzhiyun		opp-microvolt = <850000>;
168*4882a593Smuzhiyun	};
169*4882a593Smuzhiyun	opp@562500000 {
170*4882a593Smuzhiyun		opp-hz = /bits/ 64 <562500000>;
171*4882a593Smuzhiyun		opp-microvolt = <875000>;
172*4882a593Smuzhiyun	};
173*4882a593Smuzhiyun	opp@600000000 {
174*4882a593Smuzhiyun		opp-hz = /bits/ 64 <600000000>;
175*4882a593Smuzhiyun		opp-microvolt = <900000>;
176*4882a593Smuzhiyun	};
177*4882a593Smuzhiyun};
178*4882a593Smuzhiyun
179*4882a593SmuzhiyunExample for a Juno with 2 clocks and 2 regulators:
180*4882a593Smuzhiyun
181*4882a593Smuzhiyungpu_opp_table: opp_table0 {
182*4882a593Smuzhiyun	compatible = "operating-points-v2", "operating-points-v2-mali";
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun	opp@0 {
185*4882a593Smuzhiyun		opp-hz = /bits/ 64 <50000000>;
186*4882a593Smuzhiyun		opp-hz-real = /bits/ 64 <50000000>, /bits/ 64 <45000000>;
187*4882a593Smuzhiyun		opp-microvolt = <820000>, <800000>;
188*4882a593Smuzhiyun		opp-core-mask = /bits/ 64 <0xf>;
189*4882a593Smuzhiyun	};
190*4882a593Smuzhiyun	opp@1 {
191*4882a593Smuzhiyun		opp-hz = /bits/ 64 <40000000>;
192*4882a593Smuzhiyun		opp-hz-real = /bits/ 64 <40000000>, /bits/ 64 <35000000>;
193*4882a593Smuzhiyun		opp-microvolt = <720000>, <700000>;
194*4882a593Smuzhiyun		opp-core-mask = /bits/ 64 <0x7>;
195*4882a593Smuzhiyun	};
196*4882a593Smuzhiyun	opp@2 {
197*4882a593Smuzhiyun		opp-hz = /bits/ 64 <30000000>;
198*4882a593Smuzhiyun		opp-hz-real = /bits/ 64 <30000000>, /bits/ 64 <25000000>;
199*4882a593Smuzhiyun		opp-microvolt = <620000>, <700000>;
200*4882a593Smuzhiyun		opp-core-mask = /bits/ 64 <0x3>;
201*4882a593Smuzhiyun	};
202*4882a593Smuzhiyun};
203