xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/power/fsl,imx-gpcv2.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Freescale i.MX General Power Controller v2
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Andrey Smirnov <andrew.smirnov@gmail.com>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription: |
13*4882a593Smuzhiyun  The i.MX7S/D General Power Control (GPC) block contains Power Gating
14*4882a593Smuzhiyun  Control (PGC) for various power domains.
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun  Power domains contained within GPC node are generic power domain
17*4882a593Smuzhiyun  providers, documented in
18*4882a593Smuzhiyun  Documentation/devicetree/bindings/power/power-domain.yaml, which are
19*4882a593Smuzhiyun  described as subnodes of the power gating controller 'pgc' node.
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun  IP cores belonging to a power domain should contain a 'power-domains'
22*4882a593Smuzhiyun  property that is a phandle for PGC node representing the domain.
23*4882a593Smuzhiyun
24*4882a593Smuzhiyunproperties:
25*4882a593Smuzhiyun  compatible:
26*4882a593Smuzhiyun    enum:
27*4882a593Smuzhiyun      - fsl,imx7d-gpc
28*4882a593Smuzhiyun      - fsl,imx8mq-gpc
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun  reg:
31*4882a593Smuzhiyun    maxItems: 1
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun  interrupts:
34*4882a593Smuzhiyun    maxItems: 1
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun  interrupt-controller: true
37*4882a593Smuzhiyun  '#interrupt-cells':
38*4882a593Smuzhiyun    const: 3
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun  pgc:
41*4882a593Smuzhiyun    type: object
42*4882a593Smuzhiyun    description: list of power domains provided by this controller.
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun    patternProperties:
45*4882a593Smuzhiyun      "power-domain@[0-9]$":
46*4882a593Smuzhiyun        type: object
47*4882a593Smuzhiyun        properties:
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun          '#power-domain-cells':
50*4882a593Smuzhiyun            const: 0
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun          reg:
53*4882a593Smuzhiyun            description: |
54*4882a593Smuzhiyun              Power domain index. Valid values are defined in
55*4882a593Smuzhiyun              include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
56*4882a593Smuzhiyun              include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
57*4882a593Smuzhiyun            maxItems: 1
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun          clocks:
60*4882a593Smuzhiyun            description: |
61*4882a593Smuzhiyun              A number of phandles to clocks that need to be enabled during domain
62*4882a593Smuzhiyun              power-up sequencing to ensure reset propagation into devices located
63*4882a593Smuzhiyun              inside this power domain.
64*4882a593Smuzhiyun            minItems: 1
65*4882a593Smuzhiyun            maxItems: 5
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun          power-supply: true
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun        required:
70*4882a593Smuzhiyun          - '#power-domain-cells'
71*4882a593Smuzhiyun          - reg
72*4882a593Smuzhiyun
73*4882a593Smuzhiyunrequired:
74*4882a593Smuzhiyun  - compatible
75*4882a593Smuzhiyun  - reg
76*4882a593Smuzhiyun  - interrupts
77*4882a593Smuzhiyun  - pgc
78*4882a593Smuzhiyun
79*4882a593SmuzhiyunadditionalProperties: false
80*4882a593Smuzhiyun
81*4882a593Smuzhiyunexamples:
82*4882a593Smuzhiyun  - |
83*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun    gpc@303a0000 {
86*4882a593Smuzhiyun        compatible = "fsl,imx7d-gpc";
87*4882a593Smuzhiyun        reg = <0x303a0000 0x1000>;
88*4882a593Smuzhiyun        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun        pgc {
91*4882a593Smuzhiyun            #address-cells = <1>;
92*4882a593Smuzhiyun            #size-cells = <0>;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun            pgc_mipi_phy: power-domain@0 {
95*4882a593Smuzhiyun                #power-domain-cells = <0>;
96*4882a593Smuzhiyun                reg = <0>;
97*4882a593Smuzhiyun                power-supply = <&reg_1p0d>;
98*4882a593Smuzhiyun            };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun            pgc_pcie_phy: power-domain@1 {
101*4882a593Smuzhiyun                #power-domain-cells = <0>;
102*4882a593Smuzhiyun                reg = <1>;
103*4882a593Smuzhiyun                power-supply = <&reg_1p0d>;
104*4882a593Smuzhiyun            };
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun            pgc_hsic_phy: power-domain@2 {
107*4882a593Smuzhiyun                #power-domain-cells = <0>;
108*4882a593Smuzhiyun                reg = <2>;
109*4882a593Smuzhiyun                power-supply = <&reg_1p2>;
110*4882a593Smuzhiyun            };
111*4882a593Smuzhiyun        };
112*4882a593Smuzhiyun    };
113