1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale i.MX General Power Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Philipp Zabel <p.zabel@pengutronix.de> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The i.MX6 General Power Control (GPC) block contains DVFS load tracking 14*4882a593Smuzhiyun counters and Power Gating Control (PGC). 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun The power domains are generic power domain providers as documented in 17*4882a593Smuzhiyun Documentation/devicetree/bindings/power/power-domain.yaml. They are 18*4882a593Smuzhiyun described as subnodes of the power gating controller 'pgc' node of the GPC. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun IP cores belonging to a power domain should contain a 'power-domains' 21*4882a593Smuzhiyun property that is a phandle pointing to the power domain the device belongs 22*4882a593Smuzhiyun to. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunproperties: 25*4882a593Smuzhiyun compatible: 26*4882a593Smuzhiyun enum: 27*4882a593Smuzhiyun - fsl,imx6q-gpc 28*4882a593Smuzhiyun - fsl,imx6qp-gpc 29*4882a593Smuzhiyun - fsl,imx6sl-gpc 30*4882a593Smuzhiyun - fsl,imx6sx-gpc 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun reg: 33*4882a593Smuzhiyun maxItems: 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun interrupts: 36*4882a593Smuzhiyun maxItems: 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun clocks: 39*4882a593Smuzhiyun maxItems: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun clock-names: 42*4882a593Smuzhiyun const: ipg 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun pgc: 45*4882a593Smuzhiyun type: object 46*4882a593Smuzhiyun description: list of power domains provided by this controller. 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun patternProperties: 49*4882a593Smuzhiyun "power-domain@[0-9]$": 50*4882a593Smuzhiyun type: object 51*4882a593Smuzhiyun properties: 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun '#power-domain-cells': 54*4882a593Smuzhiyun const: 0 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun reg: 57*4882a593Smuzhiyun description: | 58*4882a593Smuzhiyun The following DOMAIN_INDEX values are valid for i.MX6Q: 59*4882a593Smuzhiyun ARM_DOMAIN 0 60*4882a593Smuzhiyun PU_DOMAIN 1 61*4882a593Smuzhiyun The following additional DOMAIN_INDEX value is valid for i.MX6SL: 62*4882a593Smuzhiyun DISPLAY_DOMAIN 2 63*4882a593Smuzhiyun The following additional DOMAIN_INDEX value is valid for i.MX6SX: 64*4882a593Smuzhiyun PCI_DOMAIN 3 65*4882a593Smuzhiyun maxItems: 1 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun clocks: 68*4882a593Smuzhiyun description: | 69*4882a593Smuzhiyun A number of phandles to clocks that need to be enabled during domain 70*4882a593Smuzhiyun power-up sequencing to ensure reset propagation into devices located 71*4882a593Smuzhiyun inside this power domain. 72*4882a593Smuzhiyun minItems: 1 73*4882a593Smuzhiyun maxItems: 7 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun power-supply: true 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun required: 78*4882a593Smuzhiyun - '#power-domain-cells' 79*4882a593Smuzhiyun - reg 80*4882a593Smuzhiyun 81*4882a593Smuzhiyunrequired: 82*4882a593Smuzhiyun - compatible 83*4882a593Smuzhiyun - reg 84*4882a593Smuzhiyun - interrupts 85*4882a593Smuzhiyun - clocks 86*4882a593Smuzhiyun - clock-names 87*4882a593Smuzhiyun - pgc 88*4882a593Smuzhiyun 89*4882a593SmuzhiyunadditionalProperties: false 90*4882a593Smuzhiyun 91*4882a593Smuzhiyunexamples: 92*4882a593Smuzhiyun - | 93*4882a593Smuzhiyun #include <dt-bindings/clock/imx6qdl-clock.h> 94*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun gpc@20dc000 { 97*4882a593Smuzhiyun compatible = "fsl,imx6q-gpc"; 98*4882a593Smuzhiyun reg = <0x020dc000 0x4000>; 99*4882a593Smuzhiyun interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 100*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_IPG>; 101*4882a593Smuzhiyun clock-names = "ipg"; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun pgc { 104*4882a593Smuzhiyun #address-cells = <1>; 105*4882a593Smuzhiyun #size-cells = <0>; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun power-domain@0 { 108*4882a593Smuzhiyun reg = <0>; 109*4882a593Smuzhiyun #power-domain-cells = <0>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun pd_pu: power-domain@1 { 113*4882a593Smuzhiyun reg = <1>; 114*4882a593Smuzhiyun #power-domain-cells = <0>; 115*4882a593Smuzhiyun power-supply = <®_pu>; 116*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, 117*4882a593Smuzhiyun <&clks IMX6QDL_CLK_GPU3D_SHADER>, 118*4882a593Smuzhiyun <&clks IMX6QDL_CLK_GPU2D_CORE>, 119*4882a593Smuzhiyun <&clks IMX6QDL_CLK_GPU2D_AXI>, 120*4882a593Smuzhiyun <&clks IMX6QDL_CLK_OPENVG_AXI>, 121*4882a593Smuzhiyun <&clks IMX6QDL_CLK_VPU_AXI>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125