1*4882a593SmuzhiyunAmlogic Meson Power Controller 2*4882a593Smuzhiyun============================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Amlogic Meson SoCs embeds an internal Power domain controller. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunVPU Power Domain 7*4882a593Smuzhiyun---------------- 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThe Video Processing Unit power domain is controlled by this power controller, 10*4882a593Smuzhiyunbut the domain requires some external resources to meet the correct power 11*4882a593Smuzhiyunsequences. 12*4882a593SmuzhiyunThe bindings must respect the power domain bindings as described in the file 13*4882a593Smuzhiyunpower-domain.yaml 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunDevice Tree Bindings: 16*4882a593Smuzhiyun--------------------- 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunRequired properties: 19*4882a593Smuzhiyun- compatible: should be one of the following : 20*4882a593Smuzhiyun - "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs 21*4882a593Smuzhiyun - "amlogic,meson-g12a-pwrc-vpu" for the Meson G12A SoCs 22*4882a593Smuzhiyun- #power-domain-cells: should be 0 23*4882a593Smuzhiyun- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node 24*4882a593Smuzhiyun- resets: phandles to the reset lines needed for this power demain sequence 25*4882a593Smuzhiyun as described in ../reset/reset.txt 26*4882a593Smuzhiyun- clocks: from common clock binding: handle to VPU and VAPB clocks 27*4882a593Smuzhiyun- clock-names: from common clock binding: must contain "vpu", "vapb" 28*4882a593Smuzhiyun corresponding to entry in the clocks property. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunParent node should have the following properties : 31*4882a593Smuzhiyun- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" 32*4882a593Smuzhiyun- reg: base address and size of the AO system control register space. 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunExample: 35*4882a593Smuzhiyun------- 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunao_sysctrl: sys-ctrl@0 { 38*4882a593Smuzhiyun compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; 39*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x100>; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun pwrc_vpu: power-controller-vpu { 42*4882a593Smuzhiyun compatible = "amlogic,meson-gx-pwrc-vpu"; 43*4882a593Smuzhiyun #power-domain-cells = <0>; 44*4882a593Smuzhiyun amlogic,hhi-sysctrl = <&sysctrl>; 45*4882a593Smuzhiyun resets = <&reset RESET_VIU>, 46*4882a593Smuzhiyun <&reset RESET_VENC>, 47*4882a593Smuzhiyun <&reset RESET_VCBUS>, 48*4882a593Smuzhiyun <&reset RESET_BT656>, 49*4882a593Smuzhiyun <&reset RESET_DVIN_RESET>, 50*4882a593Smuzhiyun <&reset RESET_RDMA>, 51*4882a593Smuzhiyun <&reset RESET_VENCI>, 52*4882a593Smuzhiyun <&reset RESET_VENCP>, 53*4882a593Smuzhiyun <&reset RESET_VDAC>, 54*4882a593Smuzhiyun <&reset RESET_VDI6>, 55*4882a593Smuzhiyun <&reset RESET_VENCL>, 56*4882a593Smuzhiyun <&reset RESET_VID_LOCK>; 57*4882a593Smuzhiyun clocks = <&clkc CLKID_VPU>, 58*4882a593Smuzhiyun <&clkc CLKID_VAPB>; 59*4882a593Smuzhiyun clock-names = "vpu", "vapb"; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun 64