1*4882a593SmuzhiyunDevice-tree bindings for persistent memory regions 2*4882a593Smuzhiyun----------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunPersistent memory refers to a class of memory devices that are: 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun a) Usable as main system memory (i.e. cacheable), and 7*4882a593Smuzhiyun b) Retain their contents across power failure. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunGiven b) it is best to think of persistent memory as a kind of memory mapped 10*4882a593Smuzhiyunstorage device. To ensure data integrity the operating system needs to manage 11*4882a593Smuzhiyunpersistent regions separately to the normal memory pool. To aid with that this 12*4882a593Smuzhiyunbinding provides a standardised interface for discovering where persistent 13*4882a593Smuzhiyunmemory regions exist inside the physical address space. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunBindings for the region nodes: 16*4882a593Smuzhiyun----------------------------- 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunRequired properties: 19*4882a593Smuzhiyun - compatible = "pmem-region" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun - reg = <base, size>; 22*4882a593Smuzhiyun The reg property should specificy an address range that is 23*4882a593Smuzhiyun translatable to a system physical address range. This address 24*4882a593Smuzhiyun range should be mappable as normal system memory would be 25*4882a593Smuzhiyun (i.e cacheable). 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun If the reg property contains multiple address ranges 28*4882a593Smuzhiyun each address range will be treated as though it was specified 29*4882a593Smuzhiyun in a separate device node. Having multiple address ranges in a 30*4882a593Smuzhiyun node implies no special relationship between the two ranges. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunOptional properties: 33*4882a593Smuzhiyun - Any relevant NUMA assocativity properties for the target platform. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun - volatile; This property indicates that this region is actually 36*4882a593Smuzhiyun backed by non-persistent memory. This lets the OS know that it 37*4882a593Smuzhiyun may skip the cache flushes required to ensure data is made 38*4882a593Smuzhiyun persistent after a write. 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun If this property is absent then the OS must assume that the region 41*4882a593Smuzhiyun is backed by non-volatile memory. 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunExamples: 44*4882a593Smuzhiyun-------------------- 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * This node specifies one 4KB region spanning from 48*4882a593Smuzhiyun * 0x5000 to 0x5fff that is backed by non-volatile memory. 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun pmem@5000 { 51*4882a593Smuzhiyun compatible = "pmem-region"; 52*4882a593Smuzhiyun reg = <0x00005000 0x00001000>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * This node specifies two 4KB regions that are backed by 57*4882a593Smuzhiyun * volatile (normal) memory. 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun pmem@6000 { 60*4882a593Smuzhiyun compatible = "pmem-region"; 61*4882a593Smuzhiyun reg = < 0x00006000 0x00001000 62*4882a593Smuzhiyun 0x00008000 0x00001000 >; 63*4882a593Smuzhiyun volatile; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66