1*4882a593Smuzhiyun* Pin configuration for TI IODELAY controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunTI dra7 based SoCs such as am57xx have a controller for setting the IO delay 4*4882a593Smuzhiyunfor each pin. For most part the IO delay values are programmed by the bootloader, 5*4882a593Smuzhiyunbut some pins need to be configured dynamically by the kernel such as the 6*4882a593SmuzhiyunMMC pins. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired Properties: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun - compatible: Must be "ti,dra7-iodelay" 11*4882a593Smuzhiyun - reg: Base address and length of the memory resource used 12*4882a593Smuzhiyun - #address-cells: Number of address cells 13*4882a593Smuzhiyun - #size-cells: Size of cells 14*4882a593Smuzhiyun - #pinctrl-cells: Number of pinctrl cells, must be 2. See also 15*4882a593Smuzhiyun Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample 18*4882a593Smuzhiyun------- 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunIn the SoC specific dtsi file: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun dra7_iodelay_core: padconf@4844a000 { 23*4882a593Smuzhiyun compatible = "ti,dra7-iodelay"; 24*4882a593Smuzhiyun reg = <0x4844a000 0x0d1c>; 25*4882a593Smuzhiyun #address-cells = <1>; 26*4882a593Smuzhiyun #size-cells = <0>; 27*4882a593Smuzhiyun #pinctrl-cells = <2>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunIn board-specific file: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&dra7_iodelay_core { 33*4882a593Smuzhiyun mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf { 34*4882a593Smuzhiyun pinctrl-pin-array = < 35*4882a593Smuzhiyun 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ 36*4882a593Smuzhiyun 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ 37*4882a593Smuzhiyun 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ 38*4882a593Smuzhiyun 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ 39*4882a593Smuzhiyun 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ 40*4882a593Smuzhiyun 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ 41*4882a593Smuzhiyun 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ 42*4882a593Smuzhiyun 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ 43*4882a593Smuzhiyun 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ 44*4882a593Smuzhiyun 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ 45*4882a593Smuzhiyun >; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun}; 48