1*4882a593Smuzhiyun* Spreadtrum Pin Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Spreadtrum pin controller are organized in 3 blocks (types). 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunThe first block comprises some global control registers, and each 6*4882a593Smuzhiyunregister contains several bit fields with one bit or several bits 7*4882a593Smuzhiyunto configure for some global common configuration, such as domain 8*4882a593Smuzhiyunpad driving level, system control select and so on ("domain pad 9*4882a593Smuzhiyundriving level": One pin can output 3.0v or 1.8v, depending on the 10*4882a593Smuzhiyunrelated domain pad driving selection, if the related domain pad 11*4882a593Smuzhiyunslect 3.0v, then the pin can output 3.0v. "system control" is used 12*4882a593Smuzhiyunto choose one function (like: UART0) for which system, since we 13*4882a593Smuzhiyunhave several systems (AP/CP/CM4) on one SoC.). 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunThere are too much various configuration that we can not list all 16*4882a593Smuzhiyunof them, so we can not make every Spreadtrum-special configuration 17*4882a593Smuzhiyunas one generic configuration, and maybe it will add more strange 18*4882a593Smuzhiyunglobal configuration in future. Then we add one "sprd,control" to 19*4882a593Smuzhiyunset these various global control configuration, and we need use 20*4882a593Smuzhiyunmagic number for this property. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunMoreover we recognise every fields comprising one bit or several 23*4882a593Smuzhiyunbits in one global control register as one pin, thus we should 24*4882a593Smuzhiyunrecord every pin's bit offset, bit width and register offset to 25*4882a593Smuzhiyunconfigure this field (pin). 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunThe second block comprises some common registers which have unified 28*4882a593Smuzhiyunregister definition, and each register described one pin is used 29*4882a593Smuzhiyunto configure the pin sleep mode, function select and sleep related 30*4882a593Smuzhiyunconfiguration. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunNow we have 4 systems for sleep mode on SC9860 SoC: AP system, 33*4882a593SmuzhiyunPUBCP system, TGLDSP system and AGDSP system. And the pin sleep 34*4882a593Smuzhiyunrelated configuration are: 35*4882a593Smuzhiyun- input-enable 36*4882a593Smuzhiyun- input-disable 37*4882a593Smuzhiyun- output-high 38*4882a593Smuzhiyun- output-low 39*4882a593Smuzhiyun- bias-pull-up 40*4882a593Smuzhiyun- bias-pull-down 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunIn some situation we need set the pin sleep mode and pin sleep related 43*4882a593Smuzhiyunconfiguration, to set the pin sleep related configuration automatically 44*4882a593Smuzhiyunby hardware when the system specified by sleep mode goes into deep 45*4882a593Smuzhiyunsleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP 46*4882a593Smuzhiyunand set the pin sleep related configuration as "input-enable", which 47*4882a593Smuzhiyunmeans when PUBCP system goes into deep sleep mode, this pin will be set 48*4882a593Smuzhiyuninput enable automatically. 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunMoreover we can not use the "sleep" state, since some systems (like: 51*4882a593SmuzhiyunPUBCP system) do not run linux kernel OS (only AP system run linux 52*4882a593Smuzhiyunkernel on SC9860 platform), then we can not select "sleep" state 53*4882a593Smuzhiyunwhen the PUBCP system goes into deep sleep mode. Thus we introduce 54*4882a593Smuzhiyun"sprd,sleep-mode" property to set pin sleep mode. 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunThe last block comprises some misc registers which also have unified 57*4882a593Smuzhiyunregister definition, and each register described one pin is used to 58*4882a593Smuzhiyunconfigure drive strength, pull up/down and so on. Especially for pull 59*4882a593Smuzhiyunup, we have two kind pull up resistor: 20K and 4.7K. 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunRequired properties for Spreadtrum pin controller: 62*4882a593Smuzhiyun- compatible: "sprd,<soc>-pinctrl" 63*4882a593Smuzhiyun Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported SoCs. 64*4882a593Smuzhiyun- reg: The register address of pin controller device. 65*4882a593Smuzhiyun- pins : An array of pin names. 66*4882a593Smuzhiyun 67*4882a593SmuzhiyunOptional properties: 68*4882a593Smuzhiyun- function: Specified the function name. 69*4882a593Smuzhiyun- drive-strength: Drive strength in mA. 70*4882a593Smuzhiyun- input-schmitt-disable: Enable schmitt-trigger mode. 71*4882a593Smuzhiyun- input-schmitt-enable: Disable schmitt-trigger mode. 72*4882a593Smuzhiyun- bias-disable: Disable pin bias. 73*4882a593Smuzhiyun- bias-pull-down: Pull down on pin. 74*4882a593Smuzhiyun- bias-pull-up: Pull up on pin. 75*4882a593Smuzhiyun- input-enable: Enable pin input. 76*4882a593Smuzhiyun- input-disable: Enable pin output. 77*4882a593Smuzhiyun- output-high: Set the pin as an output level high. 78*4882a593Smuzhiyun- output-low: Set the pin as an output level low. 79*4882a593Smuzhiyun- sleep-hardware-state: Indicate these configs in this state are sleep related. 80*4882a593Smuzhiyun- sprd,control: Control values referring to databook for global control pins. 81*4882a593Smuzhiyun- sprd,sleep-mode: Sleep mode selection. 82*4882a593Smuzhiyun 83*4882a593SmuzhiyunPlease refer to each sprd,<soc>-pinctrl.txt binding doc for supported values. 84