1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Renesas RZ/A1 combined Pin and GPIO controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Jacopo Mondi <jacopo+renesas@jmondi.org> 11*4882a593Smuzhiyun - Geert Uytterhoeven <geert+renesas@glider.be> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: 14*4882a593Smuzhiyun The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO 15*4882a593Smuzhiyun controller, named "Ports" in the hardware reference manual. 16*4882a593Smuzhiyun Pin multiplexing and GPIO configuration is performed on a per-pin basis 17*4882a593Smuzhiyun writing configuration values to per-port register sets. 18*4882a593Smuzhiyun Each "port" features up to 16 pins, each of them configurable for GPIO 19*4882a593Smuzhiyun function (port mode) or in alternate function mode. 20*4882a593Smuzhiyun Up to 8 different alternate function modes exist for each single pin. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunproperties: 23*4882a593Smuzhiyun compatible: 24*4882a593Smuzhiyun oneOf: 25*4882a593Smuzhiyun - const: renesas,r7s72100-ports # RZ/A1H 26*4882a593Smuzhiyun - items: 27*4882a593Smuzhiyun - const: renesas,r7s72101-ports # RZ/A1M 28*4882a593Smuzhiyun - const: renesas,r7s72100-ports # fallback 29*4882a593Smuzhiyun - const: renesas,r7s72102-ports # RZ/A1L 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun reg: 32*4882a593Smuzhiyun maxItems: 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyunrequired: 35*4882a593Smuzhiyun - compatible 36*4882a593Smuzhiyun - reg 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunpatternProperties: 39*4882a593Smuzhiyun "^gpio-[0-9]*$": 40*4882a593Smuzhiyun type: object 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun description: 43*4882a593Smuzhiyun Each port of the r7s72100 pin controller hardware is itself a GPIO 44*4882a593Smuzhiyun controller. 45*4882a593Smuzhiyun Different SoCs have different numbers of available pins per port, but 46*4882a593Smuzhiyun generally speaking, each of them can be configured in GPIO ("port") mode 47*4882a593Smuzhiyun on this hardware. 48*4882a593Smuzhiyun Describe GPIO controllers using sub-nodes with the following properties. 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun properties: 51*4882a593Smuzhiyun gpio-controller: true 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun '#gpio-cells': 54*4882a593Smuzhiyun const: 2 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun gpio-ranges: 57*4882a593Smuzhiyun maxItems: 1 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun required: 60*4882a593Smuzhiyun - gpio-controller 61*4882a593Smuzhiyun - '#gpio-cells' 62*4882a593Smuzhiyun - gpio-ranges 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunadditionalProperties: 66*4882a593Smuzhiyun anyOf: 67*4882a593Smuzhiyun - type: object 68*4882a593Smuzhiyun allOf: 69*4882a593Smuzhiyun - $ref: pincfg-node.yaml# 70*4882a593Smuzhiyun - $ref: pinmux-node.yaml# 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun description: 73*4882a593Smuzhiyun A pin multiplexing sub-node describes how to configure a set of (or a 74*4882a593Smuzhiyun single) pin in some desired alternate function mode. 75*4882a593Smuzhiyun A single sub-node may define several pin configurations. 76*4882a593Smuzhiyun A few alternate function require special pin configuration flags to be 77*4882a593Smuzhiyun supplied along with the alternate function configuration number. 78*4882a593Smuzhiyun The hardware reference manual specifies when a pin function requires 79*4882a593Smuzhiyun "software IO driven" mode to be specified. To do so use the generic 80*4882a593Smuzhiyun properties from the <include/linux/pinctrl/pinconf_generic.h> header 81*4882a593Smuzhiyun file to instruct the pin controller to perform the desired pin 82*4882a593Smuzhiyun configuration operation. 83*4882a593Smuzhiyun The hardware reference manual specifies when a pin has to be configured 84*4882a593Smuzhiyun to work in bi-directional mode and when the IO direction has to be 85*4882a593Smuzhiyun specified by software. Bi-directional pins must be managed by the pin 86*4882a593Smuzhiyun controller driver internally, while software driven IO direction has to 87*4882a593Smuzhiyun be explicitly selected when multiple options are available. 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun properties: 90*4882a593Smuzhiyun pinmux: 91*4882a593Smuzhiyun description: | 92*4882a593Smuzhiyun Integer array representing pin number and pin multiplexing 93*4882a593Smuzhiyun configuration. 94*4882a593Smuzhiyun When a pin has to be configured in alternate function mode, use 95*4882a593Smuzhiyun this property to identify the pin by its global index, and provide 96*4882a593Smuzhiyun its alternate function configuration number along with it. 97*4882a593Smuzhiyun When multiple pins are required to be configured as part of the 98*4882a593Smuzhiyun same alternate function they shall be specified as members of the 99*4882a593Smuzhiyun same argument list of a single "pinmux" property. 100*4882a593Smuzhiyun Helper macros to ease assembling the pin index from its position 101*4882a593Smuzhiyun (port where it sits on and pin number) and alternate function 102*4882a593Smuzhiyun identifier are provided by the pin controller header file at: 103*4882a593Smuzhiyun <include/dt-bindings/pinctrl/r7s72100-pinctrl.h> 104*4882a593Smuzhiyun Integers values in "pinmux" argument list are assembled as: 105*4882a593Smuzhiyun ((PORT * 16 + PIN) | MUX_FUNC << 16) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun phandle: true 108*4882a593Smuzhiyun input-enable: true 109*4882a593Smuzhiyun output-enable: true 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun required: 112*4882a593Smuzhiyun - pinmux 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun additionalProperties: false 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun - type: object 117*4882a593Smuzhiyun properties: 118*4882a593Smuzhiyun phandle: true 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun additionalProperties: 121*4882a593Smuzhiyun $ref: "#/additionalProperties/anyOf/0" 122*4882a593Smuzhiyun 123*4882a593Smuzhiyunexamples: 124*4882a593Smuzhiyun - | 125*4882a593Smuzhiyun #include <dt-bindings/pinctrl/r7s72100-pinctrl.h> 126*4882a593Smuzhiyun pinctrl: pinctrl@fcfe3000 { 127*4882a593Smuzhiyun compatible = "renesas,r7s72100-ports"; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun reg = <0xfcfe3000 0x4230>; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* 132*4882a593Smuzhiyun * A GPIO controller node, controlling 16 pins indexed from 0. 133*4882a593Smuzhiyun * The GPIO controller base in the global pin indexing space is pin 134*4882a593Smuzhiyun * 48, thus pins [0 - 15] on this controller map to pins [48 - 63] 135*4882a593Smuzhiyun * in the global pin indexing space. 136*4882a593Smuzhiyun */ 137*4882a593Smuzhiyun port3: gpio-3 { 138*4882a593Smuzhiyun gpio-controller; 139*4882a593Smuzhiyun #gpio-cells = <2>; 140*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 48 16>; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* 144*4882a593Smuzhiyun * A serial communication interface with a TX output pin and an RX 145*4882a593Smuzhiyun * input pin. 146*4882a593Smuzhiyun * Pin #0 on port #3 is configured as alternate function #6. 147*4882a593Smuzhiyun * Pin #2 on port #3 is configured as alternate function #4. 148*4882a593Smuzhiyun */ 149*4882a593Smuzhiyun scif2_pins: serial2 { 150*4882a593Smuzhiyun pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* 155*4882a593Smuzhiyun * I2c master: both SDA and SCL pins need bi-directional operations 156*4882a593Smuzhiyun * Pin #4 on port #1 is configured as alternate function #1. 157*4882a593Smuzhiyun * Pin #5 on port #1 is configured as alternate function #1. 158*4882a593Smuzhiyun * Both need to work in bi-directional mode, the driver must manage 159*4882a593Smuzhiyun * this internally. 160*4882a593Smuzhiyun */ 161*4882a593Smuzhiyun i2c2_pins: i2c2 { 162*4882a593Smuzhiyun pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* 167*4882a593Smuzhiyun * Multi-function timer input and output compare pins. 168*4882a593Smuzhiyun */ 169*4882a593Smuzhiyun tioc0_pins: tioc0 { 170*4882a593Smuzhiyun /* 171*4882a593Smuzhiyun * Configure TIOC0A as software driven input 172*4882a593Smuzhiyun * Pin #0 on port #4 is configured as alternate function #2 173*4882a593Smuzhiyun * with IO direction specified by software as input. 174*4882a593Smuzhiyun */ 175*4882a593Smuzhiyun tioc0_input_pins { 176*4882a593Smuzhiyun pinmux = <RZA1_PINMUX(4, 0, 2)>; 177*4882a593Smuzhiyun input-enable; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* 181*4882a593Smuzhiyun * Configure TIOC0B as software driven output 182*4882a593Smuzhiyun * Pin #1 on port #4 is configured as alternate function #1 183*4882a593Smuzhiyun * with IO direction specified by software as output. 184*4882a593Smuzhiyun */ 185*4882a593Smuzhiyun tioc0_output_pins { 186*4882a593Smuzhiyun pinmux = <RZA1_PINMUX(4, 1, 1)>; 187*4882a593Smuzhiyun output-enable; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun }; 191