1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Renesas RZ/A2 combined Pin and GPIO controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chris Brandt <chris.brandt@renesas.com> 11*4882a593Smuzhiyun - Geert Uytterhoeven <geert+renesas@glider.be> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: 14*4882a593Smuzhiyun The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO 15*4882a593Smuzhiyun controller. 16*4882a593Smuzhiyun Pin multiplexing and GPIO configuration is performed on a per-pin basis. 17*4882a593Smuzhiyun Each port features up to 8 pins, each of them configurable for GPIO function 18*4882a593Smuzhiyun (port mode) or in alternate function mode. 19*4882a593Smuzhiyun Up to 8 different alternate function modes exist for each single pin. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunproperties: 22*4882a593Smuzhiyun compatible: 23*4882a593Smuzhiyun const: "renesas,r7s9210-pinctrl" # RZ/A2M 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun gpio-controller: true 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun '#gpio-cells': 31*4882a593Smuzhiyun const: 2 32*4882a593Smuzhiyun description: 33*4882a593Smuzhiyun The first cell contains the global GPIO port index, constructed using the 34*4882a593Smuzhiyun RZA2_PIN() helper macro in r7s9210-pinctrl.h. 35*4882a593Smuzhiyun E.g. "RZA2_PIN(PORT6, 0)" for P6_0. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun gpio-ranges: 38*4882a593Smuzhiyun maxItems: 1 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunpatternProperties: 41*4882a593Smuzhiyun "^.*$": 42*4882a593Smuzhiyun if: 43*4882a593Smuzhiyun type: object 44*4882a593Smuzhiyun then: 45*4882a593Smuzhiyun allOf: 46*4882a593Smuzhiyun - $ref: pincfg-node.yaml# 47*4882a593Smuzhiyun - $ref: pinmux-node.yaml# 48*4882a593Smuzhiyun description: 49*4882a593Smuzhiyun The child nodes of the pin controller designate pins to be used for 50*4882a593Smuzhiyun specific peripheral functions or as GPIO. 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun A pin multiplexing sub-node describes how to configure a set of 53*4882a593Smuzhiyun (or a single) pin in some desired alternate function mode. 54*4882a593Smuzhiyun The values for the pinmux properties are a combination of port name, 55*4882a593Smuzhiyun pin number and the desired function index. Use the RZA2_PINMUX macro 56*4882a593Smuzhiyun located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily 57*4882a593Smuzhiyun define these. 58*4882a593Smuzhiyun For assigning GPIO pins, use the macro RZA2_PIN also in 59*4882a593Smuzhiyun to express the desired port pin. 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun properties: 62*4882a593Smuzhiyun phandle: true 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun pinmux: 65*4882a593Smuzhiyun description: 66*4882a593Smuzhiyun Values are constructed from GPIO port number, pin number, and 67*4882a593Smuzhiyun alternate function configuration number using the RZA2_PINMUX() 68*4882a593Smuzhiyun helper macro in r7s9210-pinctrl.h. 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun required: 71*4882a593Smuzhiyun - pinmux 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun additionalProperties: false 74*4882a593Smuzhiyun 75*4882a593Smuzhiyunrequired: 76*4882a593Smuzhiyun - compatible 77*4882a593Smuzhiyun - reg 78*4882a593Smuzhiyun - gpio-controller 79*4882a593Smuzhiyun - '#gpio-cells' 80*4882a593Smuzhiyun - gpio-ranges 81*4882a593Smuzhiyun 82*4882a593SmuzhiyunadditionalProperties: false 83*4882a593Smuzhiyun 84*4882a593Smuzhiyunexamples: 85*4882a593Smuzhiyun - | 86*4882a593Smuzhiyun #include <dt-bindings/pinctrl/r7s9210-pinctrl.h> 87*4882a593Smuzhiyun pinctrl: pinctrl@fcffe000 { 88*4882a593Smuzhiyun compatible = "renesas,r7s9210-pinctrl"; 89*4882a593Smuzhiyun reg = <0xfcffe000 0x1000>; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun gpio-controller; 92*4882a593Smuzhiyun #gpio-cells = <2>; 93*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 0 176>; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Serial Console */ 96*4882a593Smuzhiyun scif4_pins: serial4 { 97*4882a593Smuzhiyun pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */ 98*4882a593Smuzhiyun <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */ 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun }; 101