xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunQualcomm MSM8916 TLMM block
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThis binding describes the Top Level Mode Multiplexer block found in the
4*4882a593SmuzhiyunMSM8916 platform.
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun- compatible:
7*4882a593Smuzhiyun	Usage: required
8*4882a593Smuzhiyun	Value type: <string>
9*4882a593Smuzhiyun	Definition: must be "qcom,msm8916-pinctrl"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun- reg:
12*4882a593Smuzhiyun	Usage: required
13*4882a593Smuzhiyun	Value type: <prop-encoded-array>
14*4882a593Smuzhiyun	Definition: the base address and size of the TLMM register space.
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun- interrupts:
17*4882a593Smuzhiyun	Usage: required
18*4882a593Smuzhiyun	Value type: <prop-encoded-array>
19*4882a593Smuzhiyun	Definition: should specify the TLMM summary IRQ.
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun- interrupt-controller:
22*4882a593Smuzhiyun	Usage: required
23*4882a593Smuzhiyun	Value type: <none>
24*4882a593Smuzhiyun	Definition: identifies this node as an interrupt controller
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun- #interrupt-cells:
27*4882a593Smuzhiyun	Usage: required
28*4882a593Smuzhiyun	Value type: <u32>
29*4882a593Smuzhiyun	Definition: must be 2. Specifying the pin number and flags, as defined
30*4882a593Smuzhiyun		    in <dt-bindings/interrupt-controller/irq.h>
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun- gpio-controller:
33*4882a593Smuzhiyun	Usage: required
34*4882a593Smuzhiyun	Value type: <none>
35*4882a593Smuzhiyun	Definition: identifies this node as a gpio controller
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun- #gpio-cells:
38*4882a593Smuzhiyun	Usage: required
39*4882a593Smuzhiyun	Value type: <u32>
40*4882a593Smuzhiyun	Definition: must be 2. Specifying the pin number and flags, as defined
41*4882a593Smuzhiyun		    in <dt-bindings/gpio/gpio.h>
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun- gpio-ranges:
44*4882a593Smuzhiyun	Usage: required
45*4882a593Smuzhiyun	Definition:  see ../gpio/gpio.txt
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun- gpio-reserved-ranges:
48*4882a593Smuzhiyun	Usage: optional
49*4882a593Smuzhiyun	Definition: see ../gpio/gpio.txt
50*4882a593Smuzhiyun
51*4882a593SmuzhiyunPlease refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
52*4882a593Smuzhiyuna general description of GPIO and interrupt bindings.
53*4882a593Smuzhiyun
54*4882a593SmuzhiyunPlease refer to pinctrl-bindings.txt in this directory for details of the
55*4882a593Smuzhiyuncommon pinctrl bindings used by client devices, including the meaning of the
56*4882a593Smuzhiyunphrase "pin configuration node".
57*4882a593Smuzhiyun
58*4882a593SmuzhiyunThe pin configuration nodes act as a container for an arbitrary number of
59*4882a593Smuzhiyunsubnodes. Each of these subnodes represents some desired configuration for a
60*4882a593Smuzhiyunpin, a group, or a list of pins or groups. This configuration can include the
61*4882a593Smuzhiyunmux function to select on those pin(s)/group(s), and various pin configuration
62*4882a593Smuzhiyunparameters, such as pull-up, drive strength, etc.
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun
65*4882a593SmuzhiyunPIN CONFIGURATION NODES:
66*4882a593Smuzhiyun
67*4882a593SmuzhiyunThe name of each subnode is not important; all subnodes should be enumerated
68*4882a593Smuzhiyunand processed purely based on their content.
69*4882a593Smuzhiyun
70*4882a593SmuzhiyunEach subnode only affects those parameters that are explicitly listed. In
71*4882a593Smuzhiyunother words, a subnode that lists a mux function but no pin configuration
72*4882a593Smuzhiyunparameters implies no information about any pin configuration parameters.
73*4882a593SmuzhiyunSimilarly, a pin subnode that describes a pullup parameter implies no
74*4882a593Smuzhiyuninformation about e.g. the mux function.
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun
77*4882a593SmuzhiyunThe following generic properties as defined in pinctrl-bindings.txt are valid
78*4882a593Smuzhiyunto specify in a pin configuration subnode:
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun- pins:
81*4882a593Smuzhiyun	Usage: required
82*4882a593Smuzhiyun	Value type: <string-array>
83*4882a593Smuzhiyun	Definition: List of gpio pins affected by the properties specified in
84*4882a593Smuzhiyun		    this subnode.  Valid pins are:
85*4882a593Smuzhiyun		    gpio0-gpio121,
86*4882a593Smuzhiyun		    sdc1_clk,
87*4882a593Smuzhiyun		    sdc1_cmd,
88*4882a593Smuzhiyun		    sdc1_data
89*4882a593Smuzhiyun		    sdc2_clk,
90*4882a593Smuzhiyun		    sdc2_cmd,
91*4882a593Smuzhiyun		    sdc2_data,
92*4882a593Smuzhiyun		    qdsd_cmd,
93*4882a593Smuzhiyun		    qdsd_data0,
94*4882a593Smuzhiyun		    qdsd_data1,
95*4882a593Smuzhiyun		    qdsd_data2,
96*4882a593Smuzhiyun		    qdsd_data3
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun- function:
99*4882a593Smuzhiyun	Usage: required
100*4882a593Smuzhiyun	Value type: <string>
101*4882a593Smuzhiyun	Definition: Specify the alternative function to be configured for the
102*4882a593Smuzhiyun		    specified pins. Functions are only valid for gpio pins.
103*4882a593Smuzhiyun		    Valid values are:
104*4882a593Smuzhiyun	adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
105*4882a593Smuzhiyun	atest_char1, atest_char2, atest_char3, atest_combodac, atest_gpsadc0,
106*4882a593Smuzhiyun	atest_gpsadc1, atest_tsens, atest_wlan0, atest_wlan1, backlight_en,
107*4882a593Smuzhiyun	bimc_dte0,bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,
108*4882a593Smuzhiyun	blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2,
109*4882a593Smuzhiyun	blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3,
110*4882a593Smuzhiyun	blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4,
111*4882a593Smuzhiyun	blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2,
112*4882a593Smuzhiyun	cam1_rst, cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c,
113*4882a593Smuzhiyun	cci_timer0, cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out,
114*4882a593Smuzhiyun	display_5v, dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us,
115*4882a593Smuzhiyun	ext_lpass, flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
116*4882a593Smuzhiyun	gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gpio, gsm0_tx0, gsm0_tx1,
117*4882a593Smuzhiyun	gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, kpsns1, kpsns2, ldo_en,
118*4882a593Smuzhiyun	ldo_update, mag_int, mdp_vsync, modem_tsync, m_voc, nav_pps, nav_tsync,
119*4882a593Smuzhiyun	pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_ws, prng_rosc,
120*4882a593Smuzhiyun	pwr_crypto_enabled_a, pwr_crypto_enabled_b, pwr_modem_enabled_a,
121*4882a593Smuzhiyun	pwr_modem_enabled_b, pwr_nav_enabled_a, pwr_nav_enabled_b,
122*4882a593Smuzhiyun	qdss_ctitrig_in_a0, qdss_ctitrig_in_a1, qdss_ctitrig_in_b0,
123*4882a593Smuzhiyun	qdss_ctitrig_in_b1, qdss_ctitrig_out_a0, qdss_ctitrig_out_a1,
124*4882a593Smuzhiyun	qdss_ctitrig_out_b0, qdss_ctitrig_out_b1, qdss_traceclk_a,
125*4882a593Smuzhiyun	qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
126*4882a593Smuzhiyun	qdss_tracedata_b, reset_n, sd_card, sd_write, sec_mi2s, smb_int,
127*4882a593Smuzhiyun	ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3, uim_batt, wcss_bt, wcss_fm,
128*4882a593Smuzhiyun	wcss_wlan, webcam1_rst
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun- bias-disable:
131*4882a593Smuzhiyun	Usage: optional
132*4882a593Smuzhiyun	Value type: <none>
133*4882a593Smuzhiyun	Definition: The specified pins should be configured as no pull.
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun- bias-pull-down:
136*4882a593Smuzhiyun	Usage: optional
137*4882a593Smuzhiyun	Value type: <none>
138*4882a593Smuzhiyun	Definition: The specified pins should be configured as pull down.
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun- bias-pull-up:
141*4882a593Smuzhiyun	Usage: optional
142*4882a593Smuzhiyun	Value type: <none>
143*4882a593Smuzhiyun	Definition: The specified pins should be configured as pull up.
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun- output-high:
146*4882a593Smuzhiyun	Usage: optional
147*4882a593Smuzhiyun	Value type: <none>
148*4882a593Smuzhiyun	Definition: The specified pins are configured in output mode, driven
149*4882a593Smuzhiyun		    high.
150*4882a593Smuzhiyun		    Not valid for sdc pins.
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun- output-low:
153*4882a593Smuzhiyun	Usage: optional
154*4882a593Smuzhiyun	Value type: <none>
155*4882a593Smuzhiyun	Definition: The specified pins are configured in output mode, driven
156*4882a593Smuzhiyun		    low.
157*4882a593Smuzhiyun		    Not valid for sdc pins.
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun- drive-strength:
160*4882a593Smuzhiyun	Usage: optional
161*4882a593Smuzhiyun	Value type: <u32>
162*4882a593Smuzhiyun	Definition: Selects the drive strength for the specified pins, in mA.
163*4882a593Smuzhiyun		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
164*4882a593Smuzhiyun
165*4882a593SmuzhiyunExample:
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun	tlmm: pinctrl@1000000 {
168*4882a593Smuzhiyun		compatible = "qcom,msm8916-pinctrl";
169*4882a593Smuzhiyun		reg = <0x1000000 0x300000>;
170*4882a593Smuzhiyun		interrupts = <0 208 0>;
171*4882a593Smuzhiyun		gpio-controller;
172*4882a593Smuzhiyun		#gpio-cells = <2>;
173*4882a593Smuzhiyun		gpio-ranges = <&tlmm 0 0 122>;
174*4882a593Smuzhiyun		interrupt-controller;
175*4882a593Smuzhiyun		#interrupt-cells = <2>;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun		uart2: uart2-default {
178*4882a593Smuzhiyun			mux {
179*4882a593Smuzhiyun				pins = "gpio4", "gpio5";
180*4882a593Smuzhiyun				function = "blsp_uart2";
181*4882a593Smuzhiyun			};
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun			tx {
184*4882a593Smuzhiyun				pins = "gpio4";
185*4882a593Smuzhiyun				drive-strength = <4>;
186*4882a593Smuzhiyun				bias-disable;
187*4882a593Smuzhiyun			};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun			rx {
190*4882a593Smuzhiyun				pins = "gpio5";
191*4882a593Smuzhiyun				drive-strength = <2>;
192*4882a593Smuzhiyun				bias-pull-up;
193*4882a593Smuzhiyun			};
194*4882a593Smuzhiyun		};
195*4882a593Smuzhiyun	};
196