1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pinctrl/qcom,ipq6018-pinctrl.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Technologies, Inc. IPQ6018 TLMM block 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Sricharan R <sricharan@codeaurora.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun This binding describes the Top Level Mode Multiplexer block found in the 14*4882a593Smuzhiyun IPQ6018 platform. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: qcom,ipq6018-pinctrl 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun maxItems: 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun interrupts: 24*4882a593Smuzhiyun description: Specifies the TLMM summary IRQ 25*4882a593Smuzhiyun maxItems: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun interrupt-controller: true 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun '#interrupt-cells': 30*4882a593Smuzhiyun description: 31*4882a593Smuzhiyun Specifies the PIN numbers and Flags, as defined in defined in 32*4882a593Smuzhiyun include/dt-bindings/interrupt-controller/irq.h 33*4882a593Smuzhiyun const: 2 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun gpio-controller: true 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun '#gpio-cells': 38*4882a593Smuzhiyun description: Specifying the pin number and flags, as defined in 39*4882a593Smuzhiyun include/dt-bindings/gpio/gpio.h 40*4882a593Smuzhiyun const: 2 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun gpio-ranges: 43*4882a593Smuzhiyun maxItems: 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun#PIN CONFIGURATION NODES 46*4882a593SmuzhiyunpatternProperties: 47*4882a593Smuzhiyun '-pinmux$': 48*4882a593Smuzhiyun type: object 49*4882a593Smuzhiyun description: 50*4882a593Smuzhiyun Pinctrl node's client devices use subnodes for desired pin configuration. 51*4882a593Smuzhiyun Client device subnodes use below standard properties. 52*4882a593Smuzhiyun $ref: "/schemas/pinctrl/pincfg-node.yaml" 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun properties: 55*4882a593Smuzhiyun pins: 56*4882a593Smuzhiyun description: 57*4882a593Smuzhiyun List of gpio pins affected by the properties specified in this 58*4882a593Smuzhiyun subnode. 59*4882a593Smuzhiyun items: 60*4882a593Smuzhiyun oneOf: 61*4882a593Smuzhiyun - pattern: "^gpio([1-9]|[1-7][0-9]|80)$" 62*4882a593Smuzhiyun - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, 63*4882a593Smuzhiyun sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, 64*4882a593Smuzhiyun qdsd_data3 ] 65*4882a593Smuzhiyun minItems: 1 66*4882a593Smuzhiyun maxItems: 4 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun function: 69*4882a593Smuzhiyun description: 70*4882a593Smuzhiyun Specify the alternative function to be configured for the specified 71*4882a593Smuzhiyun pins. 72*4882a593Smuzhiyun enum: [ adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, 73*4882a593Smuzhiyun atest_char0, atest_char1, atest_char2, atest_char3, atest_combodac, 74*4882a593Smuzhiyun atest_gpsadc0, atest_gpsadc1, atest_tsens, atest_wlan0, 75*4882a593Smuzhiyun atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, blsp1_i2c, 76*4882a593Smuzhiyun blsp2_i2c, blsp3_i2c, blsp4_i2c, blsp5_i2c, blsp6_i2c, blsp1_spi, 77*4882a593Smuzhiyun blsp1_spi_cs1, blsp1_spi_cs2, blsp1_spi_cs3, blsp2_spi, 78*4882a593Smuzhiyun blsp2_spi_cs1, blsp2_spi_cs2, blsp2_spi_cs3, blsp3_spi, 79*4882a593Smuzhiyun blsp3_spi_cs1, blsp3_spi_cs2, blsp3_spi_cs3, blsp4_spi, blsp5_spi, 80*4882a593Smuzhiyun blsp6_spi, blsp1_uart, blsp2_uart, blsp1_uim, blsp2_uim, cam1_rst, 81*4882a593Smuzhiyun cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0, 82*4882a593Smuzhiyun cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, display_5v, 83*4882a593Smuzhiyun dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us, ext_lpass, 84*4882a593Smuzhiyun flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, 85*4882a593Smuzhiyun gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gpio, gsm0_tx0, 86*4882a593Smuzhiyun gsm0_tx1, gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, kpsns1, kpsns2, 87*4882a593Smuzhiyun ldo_en, ldo_update, mag_int, mdp_vsync, modem_tsync, m_voc, 88*4882a593Smuzhiyun nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, 89*4882a593Smuzhiyun pri_mi2s_ws, prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b, 90*4882a593Smuzhiyun pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a, 91*4882a593Smuzhiyun pwr_nav_enabled_b, qdss_ctitrig_in_a0, qdss_ctitrig_in_a1, 92*4882a593Smuzhiyun qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0, 93*4882a593Smuzhiyun qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1, 94*4882a593Smuzhiyun qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, 95*4882a593Smuzhiyun qdss_tracedata_a, qdss_tracedata_b, reset_n, sd_card, sd_write, 96*4882a593Smuzhiyun sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3, 97*4882a593Smuzhiyun uim_batt, wcss_bt, wcss_fm, wcss_wlan, webcam1_rst ] 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun drive-strength: 100*4882a593Smuzhiyun enum: [2, 4, 6, 8, 10, 12, 14, 16] 101*4882a593Smuzhiyun default: 2 102*4882a593Smuzhiyun description: 103*4882a593Smuzhiyun Selects the drive strength for the specified pins, in mA. 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun bias-pull-down: true 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun bias-pull-up: true 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun bias-disable: true 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun output-high: true 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun output-low: true 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun required: 116*4882a593Smuzhiyun - pins 117*4882a593Smuzhiyun - function 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun additionalProperties: false 120*4882a593Smuzhiyun 121*4882a593Smuzhiyunrequired: 122*4882a593Smuzhiyun - compatible 123*4882a593Smuzhiyun - reg 124*4882a593Smuzhiyun - interrupts 125*4882a593Smuzhiyun - interrupt-controller 126*4882a593Smuzhiyun - '#interrupt-cells' 127*4882a593Smuzhiyun - gpio-controller 128*4882a593Smuzhiyun - '#gpio-cells' 129*4882a593Smuzhiyun - gpio-ranges 130*4882a593Smuzhiyun 131*4882a593SmuzhiyunadditionalProperties: false 132*4882a593Smuzhiyun 133*4882a593Smuzhiyunexamples: 134*4882a593Smuzhiyun - | 135*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 136*4882a593Smuzhiyun tlmm: pinctrl@1000000 { 137*4882a593Smuzhiyun compatible = "qcom,ipq6018-pinctrl"; 138*4882a593Smuzhiyun reg = <0x01000000 0x300000>; 139*4882a593Smuzhiyun interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 140*4882a593Smuzhiyun interrupt-controller; 141*4882a593Smuzhiyun #interrupt-cells = <2>; 142*4882a593Smuzhiyun gpio-controller; 143*4882a593Smuzhiyun #gpio-cells = <2>; 144*4882a593Smuzhiyun gpio-ranges = <&tlmm 0 80>; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun serial3-pinmux { 147*4882a593Smuzhiyun pins = "gpio44", "gpio45"; 148*4882a593Smuzhiyun function = "blsp2_uart"; 149*4882a593Smuzhiyun drive-strength = <8>; 150*4882a593Smuzhiyun bias-pull-down; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun }; 153