xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunQualcomm QCS404 TLMM block
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThis binding describes the Top Level Mode Multiplexer block found in the
4*4882a593SmuzhiyunQCS404 platform.
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun- compatible:
7*4882a593Smuzhiyun	Usage: required
8*4882a593Smuzhiyun	Value type: <string>
9*4882a593Smuzhiyun	Definition: must be "qcom,qcs404-pinctrl"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun- reg:
12*4882a593Smuzhiyun	Usage: required
13*4882a593Smuzhiyun	Value type: <prop-encoded-array>
14*4882a593Smuzhiyun	Definition: the base address and size of the north, south and east TLMM
15*4882a593Smuzhiyun		    tiles.
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun- reg-names:
18*4882a593Smuzhiyun	Usage: required
19*4882a593Smuzhiyun	Value type: <stringlist>
20*4882a593Smuzhiyun	Defintiion: names for the cells of reg, must contain "north", "south"
21*4882a593Smuzhiyun		    and "east".
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun- interrupts:
24*4882a593Smuzhiyun	Usage: required
25*4882a593Smuzhiyun	Value type: <prop-encoded-array>
26*4882a593Smuzhiyun	Definition: should specify the TLMM summary IRQ.
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun- interrupt-controller:
29*4882a593Smuzhiyun	Usage: required
30*4882a593Smuzhiyun	Value type: <none>
31*4882a593Smuzhiyun	Definition: identifies this node as an interrupt controller
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun- #interrupt-cells:
34*4882a593Smuzhiyun	Usage: required
35*4882a593Smuzhiyun	Value type: <u32>
36*4882a593Smuzhiyun	Definition: must be 2. Specifying the pin number and flags, as defined
37*4882a593Smuzhiyun		    in <dt-bindings/interrupt-controller/irq.h>
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun- gpio-controller:
40*4882a593Smuzhiyun	Usage: required
41*4882a593Smuzhiyun	Value type: <none>
42*4882a593Smuzhiyun	Definition: identifies this node as a gpio controller
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun- #gpio-cells:
45*4882a593Smuzhiyun	Usage: required
46*4882a593Smuzhiyun	Value type: <u32>
47*4882a593Smuzhiyun	Definition: must be 2. Specifying the pin number and flags, as defined
48*4882a593Smuzhiyun		    in <dt-bindings/gpio/gpio.h>
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun- gpio-ranges:
51*4882a593Smuzhiyun	Usage: required
52*4882a593Smuzhiyun	Definition:  see ../gpio/gpio.txt
53*4882a593Smuzhiyun
54*4882a593SmuzhiyunPlease refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
55*4882a593Smuzhiyuna general description of GPIO and interrupt bindings.
56*4882a593Smuzhiyun
57*4882a593SmuzhiyunPlease refer to pinctrl-bindings.txt in this directory for details of the
58*4882a593Smuzhiyuncommon pinctrl bindings used by client devices, including the meaning of the
59*4882a593Smuzhiyunphrase "pin configuration node".
60*4882a593Smuzhiyun
61*4882a593SmuzhiyunThe pin configuration nodes act as a container for an arbitrary number of
62*4882a593Smuzhiyunsubnodes. Each of these subnodes represents some desired configuration for a
63*4882a593Smuzhiyunpin, a group, or a list of pins or groups. This configuration can include the
64*4882a593Smuzhiyunmux function to select on those pin(s)/group(s), and various pin configuration
65*4882a593Smuzhiyunparameters, such as pull-up, drive strength, etc.
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun
68*4882a593SmuzhiyunPIN CONFIGURATION NODES:
69*4882a593Smuzhiyun
70*4882a593SmuzhiyunThe name of each subnode is not important; all subnodes should be enumerated
71*4882a593Smuzhiyunand processed purely based on their content.
72*4882a593Smuzhiyun
73*4882a593SmuzhiyunEach subnode only affects those parameters that are explicitly listed. In
74*4882a593Smuzhiyunother words, a subnode that lists a mux function but no pin configuration
75*4882a593Smuzhiyunparameters implies no information about any pin configuration parameters.
76*4882a593SmuzhiyunSimilarly, a pin subnode that describes a pullup parameter implies no
77*4882a593Smuzhiyuninformation about e.g. the mux function.
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun
80*4882a593SmuzhiyunThe following generic properties as defined in pinctrl-bindings.txt are valid
81*4882a593Smuzhiyunto specify in a pin configuration subnode:
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun- pins:
84*4882a593Smuzhiyun	Usage: required
85*4882a593Smuzhiyun	Value type: <string-array>
86*4882a593Smuzhiyun	Definition: List of gpio pins affected by the properties specified in
87*4882a593Smuzhiyun		    this subnode.
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun		    Valid pins are:
90*4882a593Smuzhiyun		      gpio0-gpio119
91*4882a593Smuzhiyun		        Supports mux, bias and drive-strength
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun		      sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
94*4882a593Smuzhiyun		      sdc2_data
95*4882a593Smuzhiyun		        Supports bias and drive-strength
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		      ufs_reset
98*4882a593Smuzhiyun		        Supports bias and drive-strength
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun- function:
101*4882a593Smuzhiyun	Usage: required
102*4882a593Smuzhiyun	Value type: <string>
103*4882a593Smuzhiyun	Definition: Specify the alternative function to be configured for the
104*4882a593Smuzhiyun		    specified pins. Functions are only valid for gpio pins.
105*4882a593Smuzhiyun		    Valid values are:
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun		    gpio, hdmi_tx, hdmi_ddc, blsp_uart_tx_a2, blsp_spi2, m_voc,
108*4882a593Smuzhiyun		    qdss_cti_trig_in_a0, blsp_uart_rx_a2, qdss_tracectl_a,
109*4882a593Smuzhiyun		    blsp_uart2, aud_cdc, blsp_i2c_sda_a2, qdss_tracedata_a,
110*4882a593Smuzhiyun		    blsp_i2c_scl_a2, qdss_tracectl_b, qdss_cti_trig_in_b0,
111*4882a593Smuzhiyun		    blsp_uart1, blsp_spi_mosi_a1, blsp_spi_miso_a1,
112*4882a593Smuzhiyun		    qdss_tracedata_b, blsp_i2c1, blsp_spi_cs_n_a1, gcc_plltest,
113*4882a593Smuzhiyun		    blsp_spi_clk_a1, rgb_data0, blsp_uart5, blsp_spi5,
114*4882a593Smuzhiyun		    adsp_ext, rgb_data1, prng_rosc, rgb_data2, blsp_i2c5,
115*4882a593Smuzhiyun		    gcc_gp1_clk_b, rgb_data3, gcc_gp2_clk_b, blsp_spi0,
116*4882a593Smuzhiyun		    blsp_uart0, gcc_gp3_clk_b, blsp_i2c0, qdss_traceclk_b,
117*4882a593Smuzhiyun		    pcie_clk, nfc_irq, blsp_spi4, nfc_dwl, audio_ts, rgb_data4,
118*4882a593Smuzhiyun		    spi_lcd, blsp_uart_tx_b2, gcc_gp3_clk_a, rgb_data5,
119*4882a593Smuzhiyun		    blsp_uart_rx_b2, blsp_i2c_sda_b2, blsp_i2c_scl_b2,
120*4882a593Smuzhiyun		    pwm_led11, i2s_3_data0_a, ebi2_lcd, i2s_3_data1_a,
121*4882a593Smuzhiyun		    i2s_3_data2_a, atest_char, pwm_led3, i2s_3_data3_a,
122*4882a593Smuzhiyun		    pwm_led4, i2s_4, ebi2_a, dsd_clk_b, pwm_led5, pwm_led6,
123*4882a593Smuzhiyun		    pwm_led7, pwm_led8, pwm_led24, spkr_dac0, blsp_i2c4,
124*4882a593Smuzhiyun		    pwm_led9, pwm_led10, spdifrx_opt, pwm_led12, pwm_led13,
125*4882a593Smuzhiyun		    pwm_led14, wlan1_adc1, rgb_data_b0, pwm_led15,
126*4882a593Smuzhiyun		    blsp_spi_mosi_b1, wlan1_adc0, rgb_data_b1, pwm_led16,
127*4882a593Smuzhiyun		    blsp_spi_miso_b1, qdss_cti_trig_out_b0, wlan2_adc1,
128*4882a593Smuzhiyun		    rgb_data_b2, pwm_led17, blsp_spi_cs_n_b1, wlan2_adc0,
129*4882a593Smuzhiyun		    rgb_data_b3, pwm_led18, blsp_spi_clk_b1, rgb_data_b4,
130*4882a593Smuzhiyun		    pwm_led19, ext_mclk1_b, qdss_traceclk_a, rgb_data_b5,
131*4882a593Smuzhiyun		    pwm_led20, atest_char3, i2s_3_sck_b, ldo_update, bimc_dte0,
132*4882a593Smuzhiyun		    rgb_hsync, pwm_led21, i2s_3_ws_b, dbg_out, rgb_vsync,
133*4882a593Smuzhiyun		    i2s_3_data0_b, ldo_en, hdmi_dtest, rgb_de, i2s_3_data1_b,
134*4882a593Smuzhiyun		    hdmi_lbk9, rgb_clk, atest_char1, i2s_3_data2_b, ebi_cdc,
135*4882a593Smuzhiyun		    hdmi_lbk8, rgb_mdp, atest_char0, i2s_3_data3_b, hdmi_lbk7,
136*4882a593Smuzhiyun		    rgb_data_b6, rgb_data_b7, hdmi_lbk6, rgmii_int, cri_trng1,
137*4882a593Smuzhiyun		    rgmii_wol, cri_trng0, gcc_tlmm, rgmii_ck, rgmii_tx,
138*4882a593Smuzhiyun		    hdmi_lbk5, hdmi_pixel, hdmi_rcv, hdmi_lbk4, rgmii_ctl,
139*4882a593Smuzhiyun		    ext_lpass, rgmii_rx, cri_trng, hdmi_lbk3, hdmi_lbk2,
140*4882a593Smuzhiyun		    qdss_cti_trig_out_b1, rgmii_mdio, hdmi_lbk1, rgmii_mdc,
141*4882a593Smuzhiyun		    hdmi_lbk0, ir_in, wsa_en, rgb_data6, rgb_data7,
142*4882a593Smuzhiyun		    atest_char2, ebi_ch0, blsp_uart3, blsp_spi3, sd_write,
143*4882a593Smuzhiyun		    blsp_i2c3, gcc_gp1_clk_a, qdss_cti_trig_in_b1,
144*4882a593Smuzhiyun		    gcc_gp2_clk_a, ext_mclk0, mclk_in1, i2s_1, dsd_clk_a,
145*4882a593Smuzhiyun		    qdss_cti_trig_in_a1, rgmi_dll1, pwm_led22, pwm_led23,
146*4882a593Smuzhiyun		    qdss_cti_trig_out_a0, rgmi_dll2, pwm_led1,
147*4882a593Smuzhiyun		    qdss_cti_trig_out_a1, pwm_led2, i2s_2, pll_bist,
148*4882a593Smuzhiyun		    ext_mclk1_a, mclk_in2, bimc_dte1, i2s_3_sck_a, i2s_3_ws_a
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun- bias-disable:
151*4882a593Smuzhiyun	Usage: optional
152*4882a593Smuzhiyun	Value type: <none>
153*4882a593Smuzhiyun	Definition: The specified pins should be configured as no pull.
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun- bias-pull-down:
156*4882a593Smuzhiyun	Usage: optional
157*4882a593Smuzhiyun	Value type: <none>
158*4882a593Smuzhiyun	Definition: The specified pins should be configured as pull down.
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun- bias-pull-up:
161*4882a593Smuzhiyun	Usage: optional
162*4882a593Smuzhiyun	Value type: <none>
163*4882a593Smuzhiyun	Definition: The specified pins should be configured as pull up.
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun- output-high:
166*4882a593Smuzhiyun	Usage: optional
167*4882a593Smuzhiyun	Value type: <none>
168*4882a593Smuzhiyun	Definition: The specified pins are configured in output mode, driven
169*4882a593Smuzhiyun		    high.
170*4882a593Smuzhiyun		    Not valid for sdc pins.
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun- output-low:
173*4882a593Smuzhiyun	Usage: optional
174*4882a593Smuzhiyun	Value type: <none>
175*4882a593Smuzhiyun	Definition: The specified pins are configured in output mode, driven
176*4882a593Smuzhiyun		    low.
177*4882a593Smuzhiyun		    Not valid for sdc pins.
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun- drive-strength:
180*4882a593Smuzhiyun	Usage: optional
181*4882a593Smuzhiyun	Value type: <u32>
182*4882a593Smuzhiyun	Definition: Selects the drive strength for the specified pins, in mA.
183*4882a593Smuzhiyun		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
184*4882a593Smuzhiyun
185*4882a593SmuzhiyunExample:
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun	tlmm: pinctrl@1000000 {
188*4882a593Smuzhiyun		compatible = "qcom,qcs404-pinctrl";
189*4882a593Smuzhiyun		reg = <0x01000000 0x200000>,
190*4882a593Smuzhiyun		      <0x01300000 0x200000>,
191*4882a593Smuzhiyun		      <0x07b00000 0x200000>;
192*4882a593Smuzhiyun		reg-names = "south", "north", "east";
193*4882a593Smuzhiyun		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
194*4882a593Smuzhiyun		gpio-controller;
195*4882a593Smuzhiyun		#gpio-cells = <2>;
196*4882a593Smuzhiyun		gpio-ranges = <&tlmm 0 0 120>;
197*4882a593Smuzhiyun		interrupt-controller;
198*4882a593Smuzhiyun		#interrupt-cells = <2>;
199*4882a593Smuzhiyun	};
200