1*4882a593SmuzhiyunQualcomm PMIC GPIO block 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding describes the GPIO block(s) found in the 8xxx series of 4*4882a593SmuzhiyunPMIC's from Qualcomm. 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun- compatible: 7*4882a593Smuzhiyun Usage: required 8*4882a593Smuzhiyun Value type: <string> 9*4882a593Smuzhiyun Definition: must be one of: 10*4882a593Smuzhiyun "qcom,pm8005-gpio" 11*4882a593Smuzhiyun "qcom,pm8018-gpio" 12*4882a593Smuzhiyun "qcom,pm8038-gpio" 13*4882a593Smuzhiyun "qcom,pm8058-gpio" 14*4882a593Smuzhiyun "qcom,pm8916-gpio" 15*4882a593Smuzhiyun "qcom,pm8917-gpio" 16*4882a593Smuzhiyun "qcom,pm8921-gpio" 17*4882a593Smuzhiyun "qcom,pm8941-gpio" 18*4882a593Smuzhiyun "qcom,pm8950-gpio" 19*4882a593Smuzhiyun "qcom,pm8994-gpio" 20*4882a593Smuzhiyun "qcom,pm8998-gpio" 21*4882a593Smuzhiyun "qcom,pma8084-gpio" 22*4882a593Smuzhiyun "qcom,pmi8950-gpio" 23*4882a593Smuzhiyun "qcom,pmi8994-gpio" 24*4882a593Smuzhiyun "qcom,pmi8998-gpio" 25*4882a593Smuzhiyun "qcom,pms405-gpio" 26*4882a593Smuzhiyun "qcom,pm660-gpio" 27*4882a593Smuzhiyun "qcom,pm660l-gpio" 28*4882a593Smuzhiyun "qcom,pm8150-gpio" 29*4882a593Smuzhiyun "qcom,pm8150b-gpio" 30*4882a593Smuzhiyun "qcom,pm6150-gpio" 31*4882a593Smuzhiyun "qcom,pm6150l-gpio" 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" 34*4882a593Smuzhiyun if the device is on an spmi bus or an ssbi bus respectively 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun- reg: 37*4882a593Smuzhiyun Usage: required 38*4882a593Smuzhiyun Value type: <prop-encoded-array> 39*4882a593Smuzhiyun Definition: Register base of the GPIO block and length. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun- interrupts: 42*4882a593Smuzhiyun Usage: required 43*4882a593Smuzhiyun Value type: <prop-encoded-array> 44*4882a593Smuzhiyun Definition: Must contain an array of encoded interrupt specifiers for 45*4882a593Smuzhiyun each available GPIO 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun- gpio-controller: 48*4882a593Smuzhiyun Usage: required 49*4882a593Smuzhiyun Value type: <none> 50*4882a593Smuzhiyun Definition: Mark the device node as a GPIO controller 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun- #gpio-cells: 53*4882a593Smuzhiyun Usage: required 54*4882a593Smuzhiyun Value type: <u32> 55*4882a593Smuzhiyun Definition: Must be 2; 56*4882a593Smuzhiyun the first cell will be used to define gpio number and the 57*4882a593Smuzhiyun second denotes the flags for this gpio 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunPlease refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for 60*4882a593Smuzhiyuna general description of GPIO and interrupt bindings. 61*4882a593Smuzhiyun 62*4882a593SmuzhiyunPlease refer to pinctrl-bindings.txt in this directory for details of the 63*4882a593Smuzhiyuncommon pinctrl bindings used by client devices, including the meaning of the 64*4882a593Smuzhiyunphrase "pin configuration node". 65*4882a593Smuzhiyun 66*4882a593SmuzhiyunThe pin configuration nodes act as a container for an arbitrary number of 67*4882a593Smuzhiyunsubnodes. Each of these subnodes represents some desired configuration for a 68*4882a593Smuzhiyunpin or a list of pins. This configuration can include the 69*4882a593Smuzhiyunmux function to select on those pin(s), and various pin configuration 70*4882a593Smuzhiyunparameters, as listed below. 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunSUBNODES: 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunThe name of each subnode is not important; all subnodes should be enumerated 76*4882a593Smuzhiyunand processed purely based on their content. 77*4882a593Smuzhiyun 78*4882a593SmuzhiyunEach subnode only affects those parameters that are explicitly listed. In 79*4882a593Smuzhiyunother words, a subnode that lists a mux function but no pin configuration 80*4882a593Smuzhiyunparameters implies no information about any pin configuration parameters. 81*4882a593SmuzhiyunSimilarly, a pin subnode that describes a pullup parameter implies no 82*4882a593Smuzhiyuninformation about e.g. the mux function. 83*4882a593Smuzhiyun 84*4882a593SmuzhiyunThe following generic properties as defined in pinctrl-bindings.txt are valid 85*4882a593Smuzhiyunto specify in a pin configuration subnode: 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun- pins: 88*4882a593Smuzhiyun Usage: required 89*4882a593Smuzhiyun Value type: <string-array> 90*4882a593Smuzhiyun Definition: List of gpio pins affected by the properties specified in 91*4882a593Smuzhiyun this subnode. Valid pins are: 92*4882a593Smuzhiyun gpio1-gpio4 for pm8005 93*4882a593Smuzhiyun gpio1-gpio6 for pm8018 94*4882a593Smuzhiyun gpio1-gpio12 for pm8038 95*4882a593Smuzhiyun gpio1-gpio40 for pm8058 96*4882a593Smuzhiyun gpio1-gpio4 for pm8916 97*4882a593Smuzhiyun gpio1-gpio38 for pm8917 98*4882a593Smuzhiyun gpio1-gpio44 for pm8921 99*4882a593Smuzhiyun gpio1-gpio36 for pm8941 100*4882a593Smuzhiyun gpio1-gpio8 for pm8950 (hole on gpio3) 101*4882a593Smuzhiyun gpio1-gpio22 for pm8994 102*4882a593Smuzhiyun gpio1-gpio26 for pm8998 103*4882a593Smuzhiyun gpio1-gpio22 for pma8084 104*4882a593Smuzhiyun gpio1-gpio2 for pmi8950 105*4882a593Smuzhiyun gpio1-gpio10 for pmi8994 106*4882a593Smuzhiyun gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10) 107*4882a593Smuzhiyun gpio1-gpio10 for pm8150 (holes on gpio2, gpio5, gpio7 108*4882a593Smuzhiyun and gpio8) 109*4882a593Smuzhiyun gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7) 110*4882a593Smuzhiyun gpio1-gpio12 for pm8150l (hole on gpio7) 111*4882a593Smuzhiyun gpio1-gpio10 for pm6150 112*4882a593Smuzhiyun gpio1-gpio12 for pm6150l 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun- function: 115*4882a593Smuzhiyun Usage: required 116*4882a593Smuzhiyun Value type: <string> 117*4882a593Smuzhiyun Definition: Specify the alternative function to be configured for the 118*4882a593Smuzhiyun specified pins. Valid values are: 119*4882a593Smuzhiyun "normal", 120*4882a593Smuzhiyun "paired", 121*4882a593Smuzhiyun "func1", 122*4882a593Smuzhiyun "func2", 123*4882a593Smuzhiyun "dtest1", 124*4882a593Smuzhiyun "dtest2", 125*4882a593Smuzhiyun "dtest3", 126*4882a593Smuzhiyun "dtest4", 127*4882a593Smuzhiyun And following values are supported by LV/MV GPIO subtypes: 128*4882a593Smuzhiyun "func3", 129*4882a593Smuzhiyun "func4" 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun- bias-disable: 132*4882a593Smuzhiyun Usage: optional 133*4882a593Smuzhiyun Value type: <none> 134*4882a593Smuzhiyun Definition: The specified pins should be configured as no pull. 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun- bias-pull-down: 137*4882a593Smuzhiyun Usage: optional 138*4882a593Smuzhiyun Value type: <none> 139*4882a593Smuzhiyun Definition: The specified pins should be configured as pull down. 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun- bias-pull-up: 142*4882a593Smuzhiyun Usage: optional 143*4882a593Smuzhiyun Value type: <empty> 144*4882a593Smuzhiyun Definition: The specified pins should be configured as pull up. 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun- qcom,pull-up-strength: 147*4882a593Smuzhiyun Usage: optional 148*4882a593Smuzhiyun Value type: <u32> 149*4882a593Smuzhiyun Definition: Specifies the strength to use for pull up, if selected. 150*4882a593Smuzhiyun Valid values are; as defined in 151*4882a593Smuzhiyun <dt-bindings/pinctrl/qcom,pmic-gpio.h>: 152*4882a593Smuzhiyun 1: 30uA (PMIC_GPIO_PULL_UP_30) 153*4882a593Smuzhiyun 2: 1.5uA (PMIC_GPIO_PULL_UP_1P5) 154*4882a593Smuzhiyun 3: 31.5uA (PMIC_GPIO_PULL_UP_31P5) 155*4882a593Smuzhiyun 4: 1.5uA + 30uA boost (PMIC_GPIO_PULL_UP_1P5_30) 156*4882a593Smuzhiyun If this property is omitted 30uA strength will be used if 157*4882a593Smuzhiyun pull up is selected 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun- bias-high-impedance: 160*4882a593Smuzhiyun Usage: optional 161*4882a593Smuzhiyun Value type: <none> 162*4882a593Smuzhiyun Definition: The specified pins will put in high-Z mode and disabled. 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun- input-enable: 165*4882a593Smuzhiyun Usage: optional 166*4882a593Smuzhiyun Value type: <none> 167*4882a593Smuzhiyun Definition: The specified pins are put in input mode. 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun- output-high: 170*4882a593Smuzhiyun Usage: optional 171*4882a593Smuzhiyun Value type: <none> 172*4882a593Smuzhiyun Definition: The specified pins are configured in output mode, driven 173*4882a593Smuzhiyun high. 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun- output-low: 176*4882a593Smuzhiyun Usage: optional 177*4882a593Smuzhiyun Value type: <none> 178*4882a593Smuzhiyun Definition: The specified pins are configured in output mode, driven 179*4882a593Smuzhiyun low. 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun- power-source: 182*4882a593Smuzhiyun Usage: optional 183*4882a593Smuzhiyun Value type: <u32> 184*4882a593Smuzhiyun Definition: Selects the power source for the specified pins. Valid 185*4882a593Smuzhiyun power sources are defined per chip in 186*4882a593Smuzhiyun <dt-bindings/pinctrl/qcom,pmic-gpio.h> 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun- qcom,drive-strength: 189*4882a593Smuzhiyun Usage: optional 190*4882a593Smuzhiyun Value type: <u32> 191*4882a593Smuzhiyun Definition: Selects the drive strength for the specified pins. Value 192*4882a593Smuzhiyun drive strengths are: 193*4882a593Smuzhiyun 0: no (PMIC_GPIO_STRENGTH_NO) 194*4882a593Smuzhiyun 1: high (PMIC_GPIO_STRENGTH_HIGH) 0.9mA @ 1.8V - 1.9mA @ 2.6V 195*4882a593Smuzhiyun 2: medium (PMIC_GPIO_STRENGTH_MED) 0.6mA @ 1.8V - 1.25mA @ 2.6V 196*4882a593Smuzhiyun 3: low (PMIC_GPIO_STRENGTH_LOW) 0.15mA @ 1.8V - 0.3mA @ 2.6V 197*4882a593Smuzhiyun as defined in <dt-bindings/pinctrl/qcom,pmic-gpio.h> 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun- drive-push-pull: 200*4882a593Smuzhiyun Usage: optional 201*4882a593Smuzhiyun Value type: <none> 202*4882a593Smuzhiyun Definition: The specified pins are configured in push-pull mode. 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun- drive-open-drain: 205*4882a593Smuzhiyun Usage: optional 206*4882a593Smuzhiyun Value type: <none> 207*4882a593Smuzhiyun Definition: The specified pins are configured in open-drain mode. 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun- drive-open-source: 210*4882a593Smuzhiyun Usage: optional 211*4882a593Smuzhiyun Value type: <none> 212*4882a593Smuzhiyun Definition: The specified pins are configured in open-source mode. 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun- qcom,analog-pass: 215*4882a593Smuzhiyun Usage: optional 216*4882a593Smuzhiyun Value type: <none> 217*4882a593Smuzhiyun Definition: The specified pins are configured in analog-pass-through mode. 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun- qcom,atest: 220*4882a593Smuzhiyun Usage: optional 221*4882a593Smuzhiyun Value type: <u32> 222*4882a593Smuzhiyun Definition: Selects ATEST rail to route to GPIO when it's configured 223*4882a593Smuzhiyun in analog-pass-through mode. 224*4882a593Smuzhiyun Valid values are 1-4 corresponding to ATEST1 to ATEST4. 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun- qcom,dtest-buffer: 227*4882a593Smuzhiyun Usage: optional 228*4882a593Smuzhiyun Value type: <u32> 229*4882a593Smuzhiyun Definition: Selects DTEST rail to route to GPIO when it's configured 230*4882a593Smuzhiyun as digital input. 231*4882a593Smuzhiyun Valid values are 1-4 corresponding to DTEST1 to DTEST4. 232*4882a593Smuzhiyun 233*4882a593SmuzhiyunExample: 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun pm8921_gpio: gpio@150 { 236*4882a593Smuzhiyun compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio"; 237*4882a593Smuzhiyun reg = <0x150 0x160>; 238*4882a593Smuzhiyun interrupts = <192 1>, <193 1>, <194 1>, 239*4882a593Smuzhiyun <195 1>, <196 1>, <197 1>, 240*4882a593Smuzhiyun <198 1>, <199 1>, <200 1>, 241*4882a593Smuzhiyun <201 1>, <202 1>, <203 1>, 242*4882a593Smuzhiyun <204 1>, <205 1>, <206 1>, 243*4882a593Smuzhiyun <207 1>, <208 1>, <209 1>, 244*4882a593Smuzhiyun <210 1>, <211 1>, <212 1>, 245*4882a593Smuzhiyun <213 1>, <214 1>, <215 1>, 246*4882a593Smuzhiyun <216 1>, <217 1>, <218 1>, 247*4882a593Smuzhiyun <219 1>, <220 1>, <221 1>, 248*4882a593Smuzhiyun <222 1>, <223 1>, <224 1>, 249*4882a593Smuzhiyun <225 1>, <226 1>, <227 1>, 250*4882a593Smuzhiyun <228 1>, <229 1>, <230 1>, 251*4882a593Smuzhiyun <231 1>, <232 1>, <233 1>, 252*4882a593Smuzhiyun <234 1>, <235 1>; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun gpio-controller; 255*4882a593Smuzhiyun #gpio-cells = <2>; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun pm8921_gpio_keys: gpio-keys { 258*4882a593Smuzhiyun volume-keys { 259*4882a593Smuzhiyun pins = "gpio20", "gpio21"; 260*4882a593Smuzhiyun function = "normal"; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun input-enable; 263*4882a593Smuzhiyun bias-pull-up; 264*4882a593Smuzhiyun drive-push-pull; 265*4882a593Smuzhiyun qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 266*4882a593Smuzhiyun power-source = <PM8921_GPIO_S4>; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun }; 270